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1. 发明授权

US07875530B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07875530B2
公开(公告)日：2011-01-25
申请号：US11602261
申请日：2006-11-21
申请人： Tomoko Tamura , Tomoyuki Aoki , Takuya Tsurume , Koji Dairiki
发明人： Tomoko Tamura , Tomoyuki Aoki , Takuya Tsurume , Koji Dairiki
IPC分类号： H01L21/00 , H01L21/46 , H01L21/30
CPC分类号： H01L27/1266 , H01L27/1214
摘要： First semiconductor integrated circuits and second semiconductor integrated circuits arranged over a first substrate so that each of the second semiconductor integrated circuits is adjacent to one of the first semiconductor integrated circuits are transferred to additional substrates through multiple transfer operations. After the first semiconductor integrated circuits and the second semiconductor integrated circuits formed over the first substrate are transferred to the additional substrates (a fourth substrate and a fifth substrate) respectively, the circuits are divided into a semiconductor device corresponding to each semiconductor integrated circuit. The first semiconductor integrated circuits are arranged while keeping a distance from each other over the fourth substrate, and the second semiconductor integrated circuits are arranged while keeping a distance from each other over the fifth substrate. Thus, a large division margin of each of the fourth substrate and the fifth substrate can be obtained.
摘要翻译：第一半导体集成电路和第二半导体集成电路布置在第一基板上，使得第二半导体集成电路中的每一个与第一半导体集成电路之一相邻，通过多次传送操作被传送到附加的基板。在第一半导体集成电路和形成在第一衬底上的第二半导体集成电路分别转移到附加衬底（第四衬底和第五衬底）之后，将电路分成对应于每个半导体集成电路的半导体器件。第一半导体集成电路在第四衬底上彼此保持距离的同时被布置，并且第二半导体集成电路被布置成在第五衬底上彼此保持距离。因此，可以获得第四基板和第五基板中的每一个的大分割裕度。

2. 发明授权

US07504317B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07504317B2
公开(公告)日：2009-03-17
申请号：US11600070
申请日：2006-11-16
申请人： Tomoyuki Aoki , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
发明人： Tomoyuki Aoki , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
IPC分类号： H01L21/46
CPC分类号： H01L27/1266 , H01L21/78 , H01L27/1214
摘要： It is an object to provide a manufacturing method of a semiconductor device with high reliability. A plurality of first semiconductor integrated circuits, a plurality of second semiconductor integrated circuits each of which is arranged to be adjacent to one of the first semiconductor integrated circuits, a plurality of third semiconductor integrated circuits each of which is arranged to be adjacent to one of the first semiconductor integrated circuits and one of the second semiconductor integrated circuits, and a plurality of fourth semiconductor integrated circuits each of which is arranged to be adjacent to one of the first semiconductor integrated circuits, one of the second semiconductor integrated circuits, and one of the third semiconductor integrated circuits are formed over a first substrate. The first semiconductor integrated circuits are transferred to a second substrate. A first protective layer is formed to cover the first semiconductor integrated circuits and a surface of the second substrate in the periphery of the first semiconductor integrated circuits. The second substrate and the first protective layer are divided so that the plurality of the first semiconductor integrated circuits is divided into individual pieces and part of the second substrate remains in the periphery of the first semiconductor integrated circuits. Accordingly, a semiconductor device having the first semiconductor integrated circuit is manufactured.
摘要翻译：本发明的目的是提供一种高可靠性的半导体器件的制造方法。多个第一半导体集成电路，多个第二半导体集成电路，每个第二半导体集成电路被布置为与第一半导体集成电路之一相邻，多个第三半导体集成电路被布置为与第一半导体集成电路和第二半导体集成电路之一，以及多个第四半导体集成电路，每个第四半导体集成电路被布置为与第一半导体集成电路之一相邻，第二半导体集成电路之一和第二半导体集成电路之一第三半导体集成电路形成在第一基板上。第一半导体集成电路被转移到第二衬底。形成第一保护层以覆盖第一半导体集成电路和第一半导体集成电路的周边中的第二基板的表面。第二基板和第一保护层被分割成使得多个第一半导体集成电路被分成单独的部分，并且第二基板的一部分保留在第一半导体集成电路的周围。因此，制造具有第一半导体集成电路的半导体器件。

3. 发明申请

US20070128747A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070128747A1
公开(公告)日：2007-06-07
申请号：US11602261
申请日：2006-11-21
申请人： Tomoko Tamura , Tomoyuki Aoki , Takuya Tsurume , Koji Dairiki
发明人： Tomoko Tamura , Tomoyuki Aoki , Takuya Tsurume , Koji Dairiki
IPC分类号： H01L21/00
CPC分类号： H01L27/1266 , H01L27/1214
摘要： First semiconductor integrated circuits and second semiconductor integrated circuits arranged over a first substrate so that each of the second semiconductor integrated circuits is adjacent to one of the first semiconductor integrated circuits are transferred to additional substrates through multiple transfer operations. After the first semiconductor integrated circuits and the second semiconductor integrated circuits formed over the first substrate are transferred to the additional substrates (a fourth substrate and a fifth substrate) respectively, the circuits are divided into a semiconductor device corresponding to each semiconductor integrated circuit. The first semiconductor integrated circuits are arranged while keeping a distance from each other over the fourth substrate, and the second semiconductor integrated circuits are arranged while keeping a distance from each other over the fifth substrate. Thus, a large division margin of each of the fourth substrate and the fifth substrate can be obtained.
摘要翻译：第一半导体集成电路和第二半导体集成电路布置在第一基板上，使得第二半导体集成电路中的每一个与第一半导体集成电路之一相邻，通过多次传送操作被传送到附加的基板。在第一半导体集成电路和形成在第一衬底上的第二半导体集成电路分别转移到附加衬底（第四衬底和第五衬底）之后，将电路分成对应于每个半导体集成电路的半导体器件。第一半导体集成电路在第四衬底上彼此保持距离的同时被布置，并且第二半导体集成电路被布置成在第五衬底上彼此保持距离。因此，可以获得第四基板和第五基板中的每一个的大分割裕度。

4. 发明申请

US20070128833A1 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20070128833A1
公开(公告)日：2007-06-07
申请号：US11600070
申请日：2006-11-16
申请人： Tomoyuki Aoki , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
发明人： Tomoyuki Aoki , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
IPC分类号： H01L21/00
CPC分类号： H01L27/1266 , H01L21/78 , H01L27/1214
摘要： It is an object to provide a manufacturing method of a semiconductor device with high reliability. A plurality of first semiconductor integrated circuits, a plurality of second semiconductor integrated circuits each of which is arranged to be adjacent to one of the first semiconductor integrated circuits, a plurality of third semiconductor integrated circuits each of which is arranged to be adjacent to one of the first semiconductor integrated circuits and one of the second semiconductor integrated circuits, and a plurality of fourth semiconductor integrated circuits each of which is arranged to be adjacent to one of the first semiconductor integrated circuits, one of the second semiconductor integrated circuits, and one of the third semiconductor integrated circuits are formed over a first substrate. The first semiconductor integrated circuits are transferred to a second substrate. A first protective layer is formed to cover the first semiconductor integrated circuits and a surface of the second substrate in the periphery of the first semiconductor integrated circuits. The second substrate and the first protective layer are divided so that the plurality of the first semiconductor integrated circuits is divided into individual pieces and part of the second substrate remains in the periphery of the first semiconductor integrated circuits. Accordingly, a semiconductor device having the first semiconductor integrated circuit is manufactured.
摘要翻译：本发明的目的是提供一种具有高可靠性的半导体器件的制造方法。多个第一半导体集成电路，多个第二半导体集成电路，每个第二半导体集成电路被布置为与第一半导体集成电路中的一个相邻，多个第三半导体集成电路被布置为与第一半导体集成电路和第二半导体集成电路之一，以及多个第四半导体集成电路，每个第四半导体集成电路被布置为与第一半导体集成电路之一相邻，第二半导体集成电路之一和第二半导体集成电路之一第三半导体集成电路形成在第一基板上。第一半导体集成电路被转移到第二衬底。形成第一保护层以覆盖第一半导体集成电路和第一半导体集成电路的周边中的第二基板的表面。第二基板和第一保护层被分割成使得多个第一半导体集成电路被分成单独的部分，并且第二基板的一部分保留在第一半导体集成电路的周围。因此，制造具有第一半导体集成电路的半导体器件。

5. 发明授权

US08236629B2 Method for manufacturing thin film integrated circuit, and element substrate 有权
标题翻译：薄膜集成电路和元件基板的制造方法
公开(公告)号：US08236629B2
公开(公告)日：2012-08-07
申请号：US13100316
申请日：2011-05-04
申请人： Yoshitaka Dozen , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
发明人： Yoshitaka Dozen , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
IPC分类号： H01L21/00 , H01L21/46
CPC分类号： H01L27/1266 , H01L27/1214 , H01L27/1218 , H01L27/13 , H01L27/28 , H01L29/78603 , H01L2924/3511
摘要： Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.
摘要翻译：预期由硅晶片形成的IC芯片的应用形式和需求将增加，并且需要进一步降低成本。本发明的目的是提供一种IC芯片的结构和能够以较低成本生产的方法。本发明的一个特征是使用具有金属膜的金属膜和反应物作为分离层。金属膜或具有金属的反应物的蚀刻速率高，并且除了蚀刻金属膜的化学方法或具有金属的反应物之外的物理手段可以用于本发明。因此，可以在短时间内更容易地制造IDF芯片。

6. 发明授权

US08530335B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08530335B2
公开(公告)日：2013-09-10
申请号：US13071629
申请日：2011-03-25
申请人： Tomoko Tamura , Eiji Sugiyama , Yoshitaka Dozen , Koji Dairiki , Takuya Tsurume
发明人： Tomoko Tamura , Eiji Sugiyama , Yoshitaka Dozen , Koji Dairiki , Takuya Tsurume
IPC分类号： H01L21/30 , H01L21/46 , H01L21/302 , H01L21/461 , H01L23/58
CPC分类号： H01L21/02381 , H01L21/84 , H01L27/1214 , H01L27/1266 , H01L27/13 , H01L2221/68359 , H01L2221/68368 , H01L2224/81001
摘要： A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
摘要翻译：形成在衬底上的释放层; 在剥离层上形成薄膜集成电路中的至少一个; 在薄膜集成电路中的至少一个上形成膜; 并通过使用蚀刻剂除去释放层; 因此，薄膜集成电路中的至少一个从基板剥离。半导体器件通过层压等密封剥离的薄膜集成电路而形成。

7. 发明授权

US07939385B2 Method for manufacturing thin film integrated circuit, and element substrate 有权
标题翻译：薄膜集成电路和元件基板的制造方法
公开(公告)号：US07939385B2
公开(公告)日：2011-05-10
申请号：US12255117
申请日：2008-10-21
申请人： Yoshitaka Dozen , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
发明人： Yoshitaka Dozen , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
IPC分类号： H01L21/00 , H01L21/46
CPC分类号： H01L27/1266 , H01L27/1214 , H01L27/1218 , H01L27/13 , H01L27/28 , H01L29/78603 , H01L2924/3511
摘要： Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.
摘要翻译：预期由硅晶片形成的IC芯片的应用形式和需求将增加，并且需要进一步降低成本。本发明的目的是提供一种IC芯片的结构和能够以较低成本生产的方法。本发明的一个特征是使用具有金属膜的金属膜和反应物作为分离层。金属膜或具有金属的反应物的蚀刻速率高，并且除了蚀刻金属膜的化学方法或具有金属的反应物之外的物理手段可以用于本发明。因此，可以在短时间内更容易地制造IDF芯片。

8. 发明授权

US07927971B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07927971B2
公开(公告)日：2011-04-19
申请号：US11632048
申请日：2005-07-28
申请人： Tomoko Tamura , Eiji Sugiyama , Yoshitaka Dozen , Koji Dairiki , Takuya Tsurume
发明人： Tomoko Tamura , Eiji Sugiyama , Yoshitaka Dozen , Koji Dairiki , Takuya Tsurume
IPC分类号： H01L21/30 , H01L21/46 , H01L21/302 , H01L21/461 , H01L23/58
CPC分类号： H01L21/02381 , H01L21/84 , H01L27/1214 , H01L27/1266 , H01L27/13 , H01L2221/68359 , H01L2221/68368 , H01L2224/81001
摘要： A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
摘要翻译：形成在衬底上的释放层; 在剥离层上形成薄膜集成电路中的至少一个; 在薄膜集成电路中的至少一个上形成膜; 并通过使用蚀刻剂除去释放层; 因此，薄膜集成电路中的至少一个从基板剥离。半导体器件通过层压等密封剥离的薄膜集成电路而形成。

9. 发明申请

US20050287846A1 Method for manufacturing thin film integrated circuit, and element substrate 有权
标题翻译：薄膜集成电路和元件基板的制造方法
公开(公告)号：US20050287846A1
公开(公告)日：2005-12-29
申请号：US11151230
申请日：2005-06-14
申请人： Yoshitaka Dozen , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
发明人： Yoshitaka Dozen , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
IPC分类号： H01L21/77 , H01L21/84 , H01L27/13 , H01L27/28 , H01L29/786 , H01R12/00
CPC分类号： H01L27/1266 , H01L27/1214 , H01L27/1218 , H01L27/13 , H01L27/28 , H01L29/78603 , H01L2924/3511
摘要： Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.
摘要翻译：预期由硅晶片形成的IC芯片的应用形式和需求将增加，并且需要进一步降低成本。本发明的目的是提供一种IC芯片的结构和能够以较低成本生产的方法。本发明的一个特征是使用具有金属膜的金属膜和反应物作为分离层。金属膜或具有金属的反应物的蚀刻速率高，并且除了蚀刻金属膜的化学方法或具有金属的反应物之外的物理手段可以用于本发明。因此，可以在短时间内更容易地制造IDF芯片。

10. 发明授权

US07452786B2 Method for manufacturing thin film integrated circuit, and element substrate 有权
标题翻译：薄膜集成电路和元件基板的制造方法
公开(公告)号：US07452786B2
公开(公告)日：2008-11-18
申请号：US11151230
申请日：2005-06-14
申请人： Yoshitaka Dozen , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
发明人： Yoshitaka Dozen , Tomoko Tamura , Takuya Tsurume , Koji Dairiki
IPC分类号： H01L21/336 , H01L21/00
CPC分类号： H01L27/1266 , H01L27/1214 , H01L27/1218 , H01L27/13 , H01L27/28 , H01L29/78603 , H01L2924/3511
摘要： Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.
摘要翻译：预期由硅晶片形成的IC芯片的应用形式和需求将增加，并且需要进一步降低成本。本发明的目的是提供一种IC芯片的结构和能够以较低成本生产的方法。本发明的一个特征是使用具有金属膜的金属膜和反应物作为分离层。金属膜或具有金属的反应物的蚀刻速率高，并且除了蚀刻金属膜的化学方法或具有金属的反应物之外的物理手段可以用于本发明。因此，可以在短时间内更容易地制造IDF芯片。

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