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1. 发明授权

US4796233A Bipolar-transistor type semiconductor memory device having redundancy configuration 失效
标题翻译：具有冗余配置的双极晶体管型半导体存储器件
公开(公告)号：US4796233A
公开(公告)日：1989-01-03
申请号：US788587
申请日：1985-10-17
申请人： Tomoharu Awaya , Isao Fukushi
发明人： Tomoharu Awaya , Isao Fukushi
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/84 , G11C29/842
摘要： A bipolar-transistor type semiconductor memory device including a normal memory cell array, redundancy memory cell array, a redundancy driving circuit, and a redundancy address decision circuit. When the redundancy address decision circuit determines that the input address coincides with the address of a defective circuit portion, the redundancy driving circuit is driven to enable the redundancy memory cell array instead of the normal memory cell array.
摘要翻译：包括正常存储单元阵列，冗余存储单元阵列，冗余驱动电路和冗余地址判定电路的双极晶体管型半导体存储器件。当冗余地址判定电路确定输入地址与故障电路部分的地址一致时，驱动冗余驱动电路以使冗余存储单元阵列代替正常存储单元阵列。

2. 发明授权

US4745582A Bipolar-transistor type random access memory device having redundancy configuration 失效
标题翻译：具有冗余配置的双极晶体管型随机存取存储器件
公开(公告)号：US4745582A
公开(公告)日：1988-05-17
申请号：US788458
申请日：1985-10-17
申请人： Isao Fukushi , Tomoharu Awaya
发明人： Isao Fukushi , Tomoharu Awaya
IPC分类号： G11C29/00 , G11C13/00
CPC分类号： G11C29/84 , G11C29/842
摘要： A bipolar-transistor type RAM device, particularly an ECL type RAM device, includes a memory cell array, an address receiving circuit, a normal memory cell selecting circuit, and a redundancy configuration. The redundancy configuration includes a redundancy memory cell array, a defective memory address storing circuit, an address comparing circuit, and a redundancy memory cell selecting circuit. The address comparing circuit directly receives the address signal and the defective memory address signal. The normal memory cell selecting circuit is energized when the address signal does not equal the defective memory address signal. Otherwise, the redundancy memory cell selecting circuit is energized.
摘要翻译：双极晶体管型RAM器件，特别是ECL型RAM器件，包括存储单元阵列，地址接收电路，正常存储单元选择电路和冗余配置。冗余配置包括冗余存储单元阵列，缺陷存储器地址存储电路，地址比较电路和冗余存储单元选择电路。地址比较电路直接接收地址信号和有缺陷的存储器地址信号。当地址信号不等于有缺陷的存储器地址信号时，正常的存储单元选择电路被通电。否则，冗余存储单元选择电路通电。

3. 发明授权

US07436689B2 Non-volatile semiconductor memory 有权
公开(公告)号：US07436689B2
公开(公告)日：2008-10-14
申请号：US11645537
申请日：2006-12-27
申请人： Isao Fukushi
发明人： Isao Fukushi
IPC分类号： G11C5/06
CPC分类号： G11C11/22 , G11C7/1006 , G11C7/22 , G11C2207/2245
摘要： When an address storing/comparing circuit stores no address identical to an external input address in read operation, in a main memory read data is written back to a data storing area after data read therefrom, and data indicating a sum of a predetermined value and a value of the read data is written to a history storing area after data read therefrom. In a sub memory, after data read from a history storing area, data read from the data storing area of the main memory is written to a data storing area and the data indicating the sum of the predetermined value and the value of the data read from the history storing area of the main memory is written to the history storing area, when the value of the data read from the history storing area of the main memory is larger than that of the sub memory.

4. 发明授权

US4893274A Semiconductor memory device having level converters 失效
标题翻译：具有电平转换器的半导体存储器件
公开(公告)号：US4893274A
公开(公告)日：1990-01-09
申请号：US261298
申请日：1988-10-24
申请人： Isao Fukushi
发明人： Isao Fukushi
IPC分类号： H03K19/0944 , G11C8/06 , G11C11/417 , H03K3/356 , H03K5/00 , H03K19/0185
CPC分类号： G11C8/06 , H03K19/018521 , H03K3/356104
摘要： A semiconductor memory device including a plurality of level converters, each of the level converters including a bridge circuit constituted by four MOS transistors having one type of conductivity, gates of one pair of four transistors opposing each other receiving a first signal and gates of the other pair of four transistors opposing each other receiving a signal complementary to the first signal; a pair of complementary MOS inverter circuits to which a second signal and a signal complementary to the second signal are input, respectively, the outputs of the pair of inverter circuits being connected to a first pair of connecting points positioned alternately in the bridge circuit, respectively; and a flip-flop circuit connected between a second pair of connecting points positioned alternately in the bridge circuit, to thereby output a third signal and a signal complementary to the third signal from the second pair of connecting points, resepctively.

5. 发明授权

US4958094A Emitter follower circuit with MOSFET 失效
标题翻译：发射极跟随电路与MOSFET
公开(公告)号：US4958094A
公开(公告)日：1990-09-18
申请号：US391605
申请日：1989-06-28
申请人： Yasuhiro Ishii , Isao Fukushi
发明人： Yasuhiro Ishii , Isao Fukushi
IPC分类号： H03K5/02 , H03K3/356 , H03K19/00 , H03K19/01 , H03K19/0175
CPC分类号： H03K3/356017 , H03K19/0016
摘要： In an emitter follower circuit including an emitter follower transistor (Q3, Q4), and a series-connected circuit connected to the emitter of the emitter follower transistor and including a current source (Q3, Q4) and a current source resistor, the current source resistor being formed by a MOS transistor (N4, N5), the emitter follower circuit being switched to active and inactive states by switching the state of the MOS transistor (N4, N5) by a control signal, there is provided current path means provided between the source and drain of the MOS transistor, for providing a resistance considerably larger than a resistance of the MOS transistor provided during conducting when the MOS transistor is at least cut off and passing an extremely small current passes therethrough at that time.

6. 发明授权

US4625299A Bipolar random access memory 失效
标题翻译：双极随机存取存储器
公开(公告)号：US4625299A
公开(公告)日：1986-11-25
申请号：US573610
申请日：1984-01-25
申请人： Hideaki Isogai , Isao Fukushi
发明人： Hideaki Isogai , Isao Fukushi
IPC分类号： G11C11/41 , G11C11/414 , G11C11/416 , G11C7/00
CPC分类号： G11C11/416
摘要： A semiconductor memory device used as a bipolar random access memory including a plurality of pairs of word lines, a plurality of pairs of bit lines, and a plurality of static memory cells located at the intersections of and connected between the pairs of word and bit lines. A plurality of constant current sources are selectively connected to the bit lines. A reading-writing voltage control circuit controls the potential of each bit line during the reading and writing of data and a writing current control circuit controls the current flowing to each bit line during the writing of data into the memory cell. Further, the writing current control circuit connects the constant current source to the reading-writing voltage control circuit in the writing of data to the memory cell. Accordingly, the bipolar random access memory can operate at a high speed with reduced power consumption and without unnecessary current flowing in the peripheral circuits.
摘要翻译：一种用作双极性随机存取存储器的半导体存储器件，包括多对字线，多对位线以及多个静态存储器单元，位于字与位线对之间的交叉点处并连接。多个恒流源选择性地连接到位线。读写电压控制电路在读取和写入数据期间控制每个位线的电位，并且写入电流控制电路在将数据写入存储单元期间控制流向每个位线的电流。此外，写入电流控制电路在将数据写入存储单元时将恒流源连接到读写电压控制电路。因此，双极性随机存取存储器可以以较低的功耗高速运行，并且在外围电路中不会有不必要的电流流动。

7. 发明授权

US07643325B2 Ferroelectric memory and operating method of same 有权
标题翻译：铁电存储器及其操作方法相同
公开(公告)号：US07643325B2
公开(公告)日：2010-01-05
申请号：US11896343
申请日：2007-08-31
申请人： Shingo Hagiwara , Yoshiaki Kaneko , Amane Inoue , Akihito Kumagai , Isao Fukushi
发明人： Shingo Hagiwara , Yoshiaki Kaneko , Amane Inoue , Akihito Kumagai , Isao Fukushi
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/1006
摘要： A nonvolatile decision memory unit stores decision data indicating whether data stored in the normal memory cells is true or false. An inversion control circuit sets the inverting signal to a valid level with a predetermined probability. A write circuit writes data having logic which is inverse logic of data to be rewritten to the normal memory cells and writes decision data indicating false to the decision memory unit when the inverting signal indicates a valid level. Since inverse data is rewritten at a predetermined frequency, an imprint is prevented when a read operation is executed repetitively. Moreover, since frequent repeating of reverse polarization of the ferroelectric capacitor due to a rewrite operation is prevented, deterioration of the ferroelectric capacitor due to reverse polarization is minimized. Thus, occurrence of the imprint and deterioration of characteristics in the ferroelectric capacitor is prevented, and the reliability of the ferroelectric memory is improved.
摘要翻译：非易失性判定存储单元存储指示存储在正常存储单元中的数据是真还是假的判定数据。反转控制电路以预定的概率将反相信号设置为有效电平。当反相信号指示有效电平时，写入电路将具有要被重写的数据的反逻辑的逻辑写入正常存储器单元，并将指示为假的判定数据写入判定存储器单元。由于逆数据以预定频率被重写，所以当重复执行读取操作时，防止压印。此外，由于防止了由于重写操作而导致的强电介质电容器的反向极化的频繁重复，使得极性反转引起的铁电电容器的劣化最小化。因此，防止了强电介质电容器的压印的发生和特性的劣化，提高了铁电存储器的可靠性。

8. 发明申请

US20080175034A1 Ferroelectric memory and operating method of same 有权
标题翻译：铁电存储器及其操作方法相同
公开(公告)号：US20080175034A1
公开(公告)日：2008-07-24
申请号：US11896343
申请日：2007-08-31
申请人： Shingo Hagiwara , Yoshiaki Kaneko , Amane Inoue , Akihito Kumagai , Isao Fukushi
发明人： Shingo Hagiwara , Yoshiaki Kaneko , Amane Inoue , Akihito Kumagai , Isao Fukushi
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22 , G11C7/1006
摘要： A nonvolatile decision memory unit stores decision data indicating whether data stored in the normal memory cells is true or false. An inversion control circuit sets the inverting signal to a valid level with a predetermined probability. A write circuit writes data having logic which is inverse logic of data to be rewritten to the normal memory cells and writes decision data indicating false to the decision memory unit when the inverting signal indicates a valid level. Since inverse data is rewritten at a predetermined frequency, an imprint is prevented when a read operation is executed repetitively. Moreover, since frequent repeating of reverse polarization of the ferroelectric capacitor due to a rewrite operation is prevented, deterioration of the ferroelectric capacitor due to reverse polarization is minimized. Thus, occurrence of the imprint and deterioration of characteristics in the ferroelectric capacitor is prevented, and the reliability of the ferroelectric memory is improved.
摘要翻译：非易失性判定存储单元存储指示存储在正常存储单元中的数据是真还是假的判定数据。反转控制电路以预定的概率将反相信号设置为有效电平。当反相信号指示有效电平时，写入电路将具有要被重写的数据的反逻辑的逻辑写入正常存储器单元，并将指示为假的判定数据写入判定存储器单元。由于逆数据以预定频率被重写，所以当重复执行读取操作时，防止压印。此外，由于防止了由于重写操作而导致的强电介质电容器的反向极化的频繁重复，使得极性反转引起的铁电电容器的劣化最小化。因此，防止了强电介质电容器的压印的发生和特性的劣化，提高了铁电存储器的可靠性。

9. 发明授权

US5124950A Multi-port semiconductor memory 失效
标题翻译：多端口半导体存储器
公开(公告)号：US5124950A
公开(公告)日：1992-06-23
申请号：US585891
申请日：1990-09-20
申请人： Isao Fukushi , Takashi Ozawa
发明人： Isao Fukushi , Takashi Ozawa
IPC分类号： G11C11/41 , G11C8/16
CPC分类号： G11C8/16
摘要： A multi-port semiconductor memory includes a memory cell array having a plurality of memory cells (10), a plurality of columns and rows, a write/read system, and at least one read system having sense amplifiers, each of the columns having a pair of data lines. Each of the sense amplifiers has first and second terminals connected to the pair of data lines and senses a voltage difference between the first and second terminals. The multi-port semiconductor memory also includes an address coincidence detection circuit which generates a control signal when a first address provided for writing write data into the memory cell array by the write/read system coincides with a second address provided for reading the write data by the read system. Further, the multi-port semiconductor memory includes a read control circuit which is provided in each of the sense amplifiers and which connects the first and second terminals of a corresponding one of the sense amplifies to the pair of data lines when the address coincidence detection circuit generates no control signal and which sets one of the first and second terminals to a predetermined voltage on the basis of the content of the write data while the other one of the first and second terminals is connected to a corresponding one of the pair of data lines.
摘要翻译：多端口半导体存储器包括具有多个存储单元（10），多个列和行的存储单元阵列，写/读系统和至少一个读出放大器的读取系统，每个列具有一对数据线。每个读出放大器具有连接到该对数据线的第一和第二端子，并感测第一和第二端子之间的电压差。多端口半导体存储器还包括地址一致检测电路，当通过写/读系统将写数据写入存储单元阵列的第一地址与提供用于读写写数据的第二地址一致时，产生控制信号读系统。此外，多端口半导体存储器包括读出控制电路，该读取控制电路设置在每个读出放大器中，并且当地址一致检测电路将该读出放大器中的相应一个读出放大器的第一和第二端子连接到该对数据线时不产生控制信号，并且基于写入数据的内容将第一和第二终端中的一个设置为预定电压，而第一和第二终端中的另一个连接到该对数据线中的相应一个。

10. 发明授权

US08213253B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US08213253B2
公开(公告)日：2012-07-03
申请号：US12696580
申请日：2010-01-29
申请人： Isao Fukushi
发明人： Isao Fukushi
IPC分类号： G11C7/14
CPC分类号： G11C11/22
摘要： A regular capacitor is saturated by an electric charge of a regular memory cell holding a high logic level and is not saturated by an electric charge from the regular memory cell holding a low logic level. A reference capacitor is saturated by the electric charge from a reference memory cell holding the high logic level. A differential sense amplifier differentially amplifies a difference between a regular read voltage read from the regular capacitor and a voltage which is lower by a first voltage than a reference read voltage being a saturation voltage read from the reference capacitor, and generates logic of data held in the memory cell. Accordingly, a difference between the reference voltage and the read voltage corresponding to the low logic level can be made relatively large. As a result, it is possible to improve a read margin.
摘要翻译：常规电容器由保持高逻辑电平的常规存储单元的电荷饱和，并且不被来自保持低逻辑电平的常规存储单元的电荷饱和。参考电容器由保持高逻辑电平的参考存储单元的电荷饱和。差分读出放大器差分放大从常规电容器读取的常规读取电压与低于作为从参考电容器读取的饱和电压的参考读取电压的第一电压的电压之间的差值，并产生保持在存储单元。因此，可以使参考电压与对应于低逻辑电平的读取电压之间的差相对较大。结果，可以提高读取余量。

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