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1. 发明授权

US4376985A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4376985A
公开(公告)日：1983-03-15
申请号：US179899
申请日：1980-08-20
申请人： Hideaki Isogai
发明人： Hideaki Isogai
IPC分类号： G11C11/34 , G11C11/411 , G11C11/416 , H01L21/331 , H01L21/8229 , H01L27/07 , H01L27/10 , H01L27/102 , H01L29/73 , G11C11/40 , G11C13/00
CPC分类号： G11C11/416 , G11C11/4116 , H01L27/0772 , H01L27/1025
摘要： A semiconductor memory device including memory cells, formed by a pair of multi-emitter transistors each having a collector and a base which are cross connected to each other and arranged in row and column directions, and read-out transistors, each having an emitter which is commonly connected to one of the emitters of the multi-emitter transistors, wherein the read-out transistors are arranged in each column. The multi-emitter transistors and the read out transistors are formed in patterns and the characteristics of both the multi-emitter and read-out transistors have the same variation due to a dispersion of the patterns caused by the manufacturing process.
摘要翻译：一种半导体存储器件，包括由一对多发射极晶体管形成的存储单元，每个多发射极晶体管具有彼此交叉连接并以行和列方向排列的集电极和基极，以及读出晶体管，每个具有发射极通常连接到多发射极晶体管的发射极之一，其中读出的晶体管被布置在每一列中。多发射极晶体管和读出晶体管以图案形成，并且由于制造过程引起的图案的分散，多发射极和读出晶体管的特性具有相同的变化。

2. 发明授权

US4394657A Decoder circuit 失效
标题翻译：解码电路
公开(公告)号：US4394657A
公开(公告)日：1983-07-19
申请号：US217757
申请日：1980-12-18
申请人： Hideaki Isogai , Yukio Takahashi
发明人： Hideaki Isogai , Yukio Takahashi
IPC分类号： G11C11/41 , G11C8/00 , G11C8/06 , G11C8/10 , G11C11/411 , G11C11/413 , G11C11/415 , H03K5/15 , H03K19/086 , H03M5/04 , H04Q9/00 , G11C11/40 , H03K19/01
CPC分类号： G11C8/10 , G11C11/4116 , G11C11/415 , G11C8/00 , G11C8/06 , H03K19/086 , H03K5/15
摘要： A decoder circuit comprises input gates, a logic circuit for generating an output according to input signals, an output gate for driving a word line, and a current control device for activating the output gate according to the output of the logic circuit.
摘要翻译：解码器电路包括输入门，用于根据输入信号产生输出的逻辑电路，用于驱动字线的输出门，以及根据逻辑电路的输出激活输出门的电流控制装置。

3. 发明授权

US4385370A Decoder circuit 失效
标题翻译：解码电路
公开(公告)号：US4385370A
公开(公告)日：1983-05-24
申请号：US179794
申请日：1980-08-20
申请人： Hideaki Isogai
发明人： Hideaki Isogai
IPC分类号： G11C11/413 , G11C8/10 , G11C11/415 , H03M7/00 , G11C8/02
CPC分类号： H03M7/005 , G11C11/415 , G11C8/10
摘要： A decoder circuit for a semiconductor memory device includes a plurality of input terminal gates for receiving address signal bits and for producing the same signal as well as inverted signals thereof; first decoder lines for decoding output signals of some of the input terminal gates; and diode matrices or multi-emitter transistors of which one terminal is connected to any decoder line selected from the first decoder lines, and of which another terminal is connected via a resistor to a power source and to the base of transistors which drive a group of output terminal gates. The diode matrices or multi-emitter transistors being capable of turning the transistor on or off depending upon the potential of the first decoder lines. The decoder circuit provides second decoder lines to which are connected constant current sources; emitter follower-connected transistors which are inserted between the power source and the second decoder lines, and which are turned on or off by the output signals of the remainder of the input terminal gates; and diode matrices or multi-emitter transistors of which one terminal is connected to any decoder line selected from the second decoder lines, and of which another terminal is connected via a resistor to the emitter of the transistor for driving the group of the output terminal gates and to the base of an output transistor. The diode matrices or the multi-emitter transistors being capable of turning the output transistor on or off depending upon the potential of the second decoder lines and upon the emitter potential of the transistor which drives the group of the output terminal gates.
摘要翻译：一种用于半导体存储器件的解码器电路包括用于接收地址信号位并产生相同信号的多个输入端门及其反相信号; 第一解码器线，用于解码一些输入端口的输出信号; 以及二极管阵列或多发射极晶体管，其一个端子连接到从第一解码器线选择的任何解码器线，并且其另一个端子经由电阻器连接到电源和驱动一组输出端口门。二极管阵列或多发射极晶体管能够根据第一解码器线的电位来打开或关闭晶体管。解码器电路提供连接的恒流源的第二解码器线; 射极跟随器连接的晶体管，其插入在电源和第二解码器线之间，并且由输入端子门的其余部分的输出信号导通或关断; 以及二极管阵列或多发射极晶体管，其一个端子连接到从第二解码器线选择的任何解码器线，并且另一个端子经由电阻器连接到晶体管的发射极，用于驱动输出端子组的组并输出到输出晶体管的基极。二极管阵列或多发射极晶体管能够根据第二解码器线的电位和驱动输出端子组的晶体管的发射极电位而导通或关断输出晶体管。

4. 发明授权

US4369502A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US4369502A
公开(公告)日：1983-01-18
申请号：US179900
申请日：1980-08-20
申请人： Hideaki Isogai
发明人： Hideaki Isogai
IPC分类号： G11C11/41 , G11C11/411 , G11C11/414 , G11C11/415 , G11C11/40 , G11C7/00
CPC分类号： G11C11/415 , G11C11/4116
摘要： A semiconductor memory circuit, comprising memory cells; word lines, hold lines and bit lines connected to respective memory cells; and a hold-current controlling circuit. The hold-current controlling circuit comprises identical controlling circuit elements connected to respective hold lines and a constant-current source commonly connected to the controlling circuit elements. Each of the controlling circuit elements comprises means for absorbing electric charges from respective hold lines, when corresponding word lines change from a selection status to a non-selection status, until the voltage level of the hold line reaches a full "L" or "H" level, and means for blocking a flow of electric charges from the hold line, when a corresponding word line changes from a non-selection status to a selection status, during a predetermined interval after time data switching from one memory cell to another memory cell is performed.
摘要翻译：一种半导体存储器电路，包括存储单元; 连接到各个存储单元的字线，保持线和位线; 和保持电流控制电路。保持电流控制电路包括连接到各个保持线的相同的控制电路元件和共同连接到控制电路元件的恒流源。每个控制电路元件包括用于从相应的保持线吸收电荷的装置，当对应的字线从选择状态变为非选择状态时，直到保持线的电压电平达到完全“L”或“H “电平，以及当从一个存储器单元切换到另一个存储单元的时间数据之后的预定间隔期间，当对应的字线从非选择状态改变为选择状态时，阻止来自保持线的电荷流动的装置被执行。

5. 发明授权

US4355245A Electronic circuit 失效
标题翻译：电子电路
公开(公告)号：US4355245A
公开(公告)日：1982-10-19
申请号：US137958
申请日：1980-04-07
申请人： Hideaki Isogai
发明人： Hideaki Isogai
IPC分类号： H03K19/086 , G11C11/415 , H01L27/07 , H03K17/04 , H03K17/0416 , H03K3/33
CPC分类号： G11C11/415 , H01L27/0783 , H03K17/04166
摘要： In an electronic circuit of a current switch construction in which the emitters of a first transistor and a second transistor are commonly connected to a constant-current supply, and a load resistor is connected to the collector of the first transistor, thereby to take out an output from the collector, the improvement being a pnp-type transistor, in which temporarily flows an electric current to a collector circuit of the first transistor when it is rendered non-conductive, which is inserted in a collector circuit of the second transistor.
摘要翻译：在电流开关结构的电子电路中，其中第一晶体管和第二晶体管的发射极共同连接到恒流源，并且负载电阻器连接到第一晶体管的集电极，从而取出从集电极输出，其改进是pnp型晶体管，其中当第一晶体管不导电时暂时将电流流向第一晶体管的集电极电路，其插入第二晶体管的集电极电路中。

6. 发明授权

US4349895A Decoder circuit of a semiconductor memory device 失效
标题翻译：一种半导体存储器件的解码电路
公开(公告)号：US4349895A
公开(公告)日：1982-09-14
申请号：US141932
申请日：1980-04-21
申请人： Hideaki Isogai
发明人： Hideaki Isogai
IPC分类号： G11C11/41 , G11C11/408 , G11C11/413 , G11C11/415 , H03M7/00 , G11C11/40
CPC分类号： G11C11/415 , G11C11/4087 , H03M7/005
摘要： A word driver in a decoder circuit of a semiconductor device has either a matrix of diodes or a multi-emitter transistor, each of said diodes or emitters of said multi-emitter transistor being connected between one of the decoder lines and a junction of a resistor circuit which is connected to a power source and another transistor which is connected to one of the word lines.
摘要翻译：半导体器件的解码器电路中的字驱动器具有二极管矩阵或多发射极晶体管，所述多发射极晶体管的所述二极管或发射极中的每一个连接在解码器线之一和电阻器电路，其连接到电源和连接到字线之一的另一个晶体管。

7. 发明授权

US4625299A Bipolar random access memory 失效
标题翻译：双极随机存取存储器
公开(公告)号：US4625299A
公开(公告)日：1986-11-25
申请号：US573610
申请日：1984-01-25
申请人： Hideaki Isogai , Isao Fukushi
发明人： Hideaki Isogai , Isao Fukushi
IPC分类号： G11C11/41 , G11C11/414 , G11C11/416 , G11C7/00
CPC分类号： G11C11/416
摘要： A semiconductor memory device used as a bipolar random access memory including a plurality of pairs of word lines, a plurality of pairs of bit lines, and a plurality of static memory cells located at the intersections of and connected between the pairs of word and bit lines. A plurality of constant current sources are selectively connected to the bit lines. A reading-writing voltage control circuit controls the potential of each bit line during the reading and writing of data and a writing current control circuit controls the current flowing to each bit line during the writing of data into the memory cell. Further, the writing current control circuit connects the constant current source to the reading-writing voltage control circuit in the writing of data to the memory cell. Accordingly, the bipolar random access memory can operate at a high speed with reduced power consumption and without unnecessary current flowing in the peripheral circuits.
摘要翻译：一种用作双极性随机存取存储器的半导体存储器件，包括多对字线，多对位线以及多个静态存储器单元，位于字与位线对之间的交叉点处并连接。多个恒流源选择性地连接到位线。读写电压控制电路在读取和写入数据期间控制每个位线的电位，并且写入电流控制电路在将数据写入存储单元期间控制流向每个位线的电流。此外，写入电流控制电路在将数据写入存储单元时将恒流源连接到读写电压控制电路。因此，双极性随机存取存储器可以以较低的功耗高速运行，并且在外围电路中不会有不必要的电流流动。

8. 发明授权

US4369503A Decoder circuit 失效
标题翻译：解码电路
公开(公告)号：US4369503A
公开(公告)日：1983-01-18
申请号：US232008
申请日：1981-02-06
申请人： Hideaki Isogai
发明人： Hideaki Isogai
IPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C11/415 , H03M7/00 , G11C11/40
CPC分类号： H03M7/005 , G11C11/415 , G11C8/10 , G11C8/12
摘要： A decoder circuit which receives a plurality of address signals and selects one of the n.times.m word lines for driving a semiconductor memory device. The decoder circuit includes a high level selection circuit which receives the upper address signals and produces n outputs, one of the n outputs is selected to be a high level, while the other (n-1) outputs are rendered at a low level. The decoder circuit also includes a low level selection circuit which receives the lower address signals and produces m outputs, one of the m outputs is selected to be the low level, while the other (m-1) outputs are rendered at the high level. The decoder circuit additionally includes n.times.m coupling circuits each of which receives one output from the high level selection circuit and one output from the low level selection circuit and which corresponds to one of the n.times.m word lines. Each of the coupling circuit selects the corresponding word line when the high level output from the high level selection circuit and the low level output from the low level selection circuit are simultaneously applied to the coupling circuit.
摘要翻译：一个解码器电路，其接收多个地址信号，并选择n×m个字线之一用于驱动半导体存储器件。解码器电路包括高电平选择电路，其接收高地址信号并产生n个输出，将n个输出中的一个选择为高电平，而将另一（n-1）个输出呈现为低电平。解码器电路还包括低电平选择电路，其接收较低地址信号并产生m个输出，其中m个输出被选择为低电平，而另一个（m-1）输出被呈现为高电平。解码器电路还包括n×m个耦合电路，每个耦合电路接收来自高电平选择电路的一个输出和来自低电平选择电路的一个输出，并且对应于n×m个字线之一。当从高电平选择电路输出的高电平和低电平选择电路的低电平输出同时施加到耦合电路时，每个耦合电路选择相应的字线。

9. 发明授权

US5785853A Method for accelerating revival of environment 失效
标题翻译：加速环境复兴的方法
公开(公告)号：US5785853A
公开(公告)日：1998-07-28
申请号：US738499
申请日：1996-10-28
申请人： Hideaki Isogai , Tomoteru Kawakami
发明人： Hideaki Isogai , Tomoteru Kawakami
IPC分类号： C02F1/30 , C02F3/28 , C02F11/04
CPC分类号： C02F11/04 , C02F1/30 , C02F3/28
摘要： A method and system can not only treat the sludge, harmful evacuations and so forth, to reduce load to the whole environment, but also permit recycling of those as a resource to be effectively utilized, and to quickly achieve activation of the environmental living. For this purpose, effective microorganisms are provided in an objective matter to be treated containing pollutant within a zone in the environment. The objective matter is maintained under anaerobic atmosphere. Under this condition, the effective microorganisms are activated by irradiating light and electromagnetic wave to said objective matter. A physical indicia data of said objective matter is then measured. On the basis of the physical indicia, irradiation of the light and the electromagnetic wave and anaerobic level of the anaerobic atmosphere are controlled for accelerating primary anaerobic fermenting decomposition and photosynthesis by the effective micro organisms to convert said pollutant into an organic matter useful for animals and plants.
摘要翻译：一种方法和系统不仅可以处理污泥，有害排泄物等，以减少对整个环境的负担，而且可以将那些作为有效利用的资源的回收利用，并迅速实现环境生活的激活。为此，在环境区域内含有污染物质的待处理目标物质中提供有效的微生物。目标问题是在厌氧气氛下保持。在这种条件下，有效的微生物通过向所述目标物质照射光和电磁波来活化。然后测量所述客观物质的物理标记数据。在物理标记的基础上，控制光照射和电磁波以及厌氧环境的厌氧水平，以加速有效微生物的初级厌氧发酵分解和光合作用，将所述污染物转化为有用的动物和植物。

10. 发明授权

US5714058A Apparatus for accelerating revival of environment 失效
标题翻译：加速环境复兴的装置
公开(公告)号：US5714058A
公开(公告)日：1998-02-03
申请号：US528414
申请日：1995-09-14
申请人： Hideaki Isogai , Tomoteru Kawakami
发明人： Hideaki Isogai , Tomoteru Kawakami
IPC分类号： B09C1/10 , B09B3/00 , C02F1/30 , C02F3/00 , C02F3/28 , C02F11/04
CPC分类号： C02F3/006 , C02F3/28 , Y02E50/343
摘要： A method and system can not only treat the sludge, harmful evacuations and so forth, to reduce load to the whole environment, but also permit recycling of those as a resource to be effectively utilized, and to quickly achieve activation of the environmental living. For this purpose, effective microorganisms are provided in an objective matter to be treated containing pollutant within a zone in the environment. The objective matter is maintained under anaerobic atmosphere. Under this condition, the effective microorganisms are activated by irradiating light and electromagnetic wave to said objective matter. A physical indicia data of said objective matter is then measured. On the basis of the physical indicia, irradiation of the light and the electromagnetic wave and anaerobic level of the anaerobic atmosphere are controlled for accelerating primary anaerobic fermenting decomposition and photosynthesis by the effective micro organisms to convert said pollutant into an organic matter useful for animals and plants.
摘要翻译：一种方法和系统不仅可以处理污泥，有害排泄物等，以减少对整个环境的负担，而且可以将那些作为有效利用的资源的回收利用，并迅速实现环境生活的激活。为此，在环境区域内含有污染物质的待处理目标物质中提供有效的微生物。目标问题是在厌氧气氛下保持。在这种条件下，有效的微生物通过向所述目标物质照射光和电磁波来活化。然后测量所述客观物质的物理标记数据。在物理标记的基础上，控制光照射和电磁波以及厌氧环境的厌氧水平，以加速有效微生物的初级厌氧发酵分解和光合作用，将所述污染物转化为有用的动物和植物。

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