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1. 发明授权

US10102903B1 Write process for a non volatile memory device 有权
公开(公告)号：US10102903B1
公开(公告)日：2018-10-16
申请号：US15476654
申请日：2017-03-31
申请人： Tommaso Vali , Violante Moschiano , Andrea D'Alessandro , Pranav Kalavade
发明人： Tommaso Vali , Violante Moschiano , Andrea D'Alessandro , Pranav Kalavade
IPC分类号： G11C11/34 , G11C11/56 , G11C16/10 , G11C16/34
摘要： An apparatus is described. The apparatus includes a non volatile memory device that includes a controller to implement a coarse write process for the non volatile memory device. The non volatile memory device includes storage cells to store more than two logic states, wherein, the coarse write process is to perform a verify operation early in the coarse write process to identify less responsive storage cells and provide additional charge to the less responsive storage cells as compared to non less responsive storage cells that are to be programmed to a same logical state as the less responsive storage cells without performing a following verify operation after each pulse of charge applied during the coarse write process.

2. 发明授权

US08681562B2 Memories and methods of programming memories 有权
标题翻译：记忆和程序记忆的方法
公开(公告)号：US08681562B2
公开(公告)日：2014-03-25
申请号：US13051599
申请日：2011-03-18
申请人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
发明人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C16/3459
摘要： Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.
摘要翻译：公开了用于调整存储器上部页面编程的装置和方法。在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

3. 发明申请

US20120176843A1 MEMORIES AND METHODS OF PROGRAMMING MEMORIES 有权
标题翻译：记忆和编程记忆的方法
公开(公告)号：US20120176843A1
公开(公告)日：2012-07-12
申请号：US13051599
申请日：2011-03-18
申请人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
发明人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C16/3459
摘要： Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.
摘要翻译：公开了用于调整存储器上部页面编程的装置和方法。在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

4. 发明申请

US20130272071A1 DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS 有权
标题翻译：确定记忆细胞组合的软数据
公开(公告)号：US20130272071A1
公开(公告)日：2013-10-17
申请号：US13444443
申请日：2012-04-11
申请人： Violante Moschiano , Tommaso Vali , Mark A. Hawes
发明人： Violante Moschiano , Tommaso Vali , Mark A. Hawes
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.
摘要翻译：本公开包括用于确定存储器单元的组合的软数据的装置和方法。多个实施例包括存储单元的阵列，其包括第一和第二存储单元，每个第一和第二存储器单元可编程为多个程序状态之一，其中第一和第二存储器单元的编程状态的组合对应于多个数据状态，以及耦合到阵列并被配置为确定与第一和第二存储器单元的程序状态相关联的软数据的缓冲器和/或控制器以及与对应于程序状态的组合的数据状态相关联的软数据至少部分地基于与第一和第二存储器单元的程序状态相关联的软数据。

5. 发明授权

US08395939B2 Compensation of back pattern effect in a memory device 有权
标题翻译：在存储器件中补偿背面图案效果
公开(公告)号：US08395939B2
公开(公告)日：2013-03-12
申请号：US13090754
申请日：2011-04-20
申请人： Tommaso Vali , Violante Moschiano , Giovanni Santin
发明人： Tommaso Vali , Violante Moschiano , Giovanni Santin
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译：在所公开的一个或多个实施例中，读取操作被补偿以用于背面图案效果。通过偏置字线的读取操作产生位线电流。作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。这种背面图案效果指示用于随后的读取操作以调整操作的时间。

6. 发明授权

US08233329B2 Architecture and method for memory programming 有权
标题翻译：内存编程的架构和方法
公开(公告)号：US08233329B2
公开(公告)日：2012-07-31
申请号：US12365589
申请日：2009-02-04
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

7. 发明授权

US09087594B2 Memory apparatus, systems, and methods 有权
标题翻译：内存设备，系统和方法
公开(公告)号：US09087594B2
公开(公告)日：2015-07-21
申请号：US13563314
申请日：2012-07-31
申请人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
发明人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC分类号： G11C11/34 , G11C16/04 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。对于相邻编程的侵略存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。提供附加的装置，系统和方法。

8. 发明授权

US08638624B2 Architecture and method for memory programming 有权
标题翻译：内存编程的架构和方法
公开(公告)号：US08638624B2
公开(公告)日：2014-01-28
申请号：US13561248
申请日：2012-07-30
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C7/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

9. 发明授权

US08593876B2 Sensing scheme in a memory device 有权
标题翻译：存储设备中的感应方案
公开(公告)号：US08593876B2
公开(公告)日：2013-11-26
申请号：US13085611
申请日：2011-04-13
申请人： Violante Moschiano , Giovanni Santin , Tommaso Vali
发明人： Violante Moschiano , Giovanni Santin , Tommaso Vali
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C16/26
摘要： Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current.
摘要翻译：公开了在存储器件中操作存储器件，产生存储器件中的参考电流以及感测存储器单元的数据状态的方法。一种这样的方法包括产生在读出放大器电路中使用的参考电流，以在存储器件内进行感测操作的同时管理泄漏电流。另一种这样的方法激活两个串联耦合晶体管中的一个，同时激活和去激活与第一晶体管串联耦合的第二晶体管，从而调节通过两个串联耦合的晶体管的电流并建立特定的参考电流。

10. 发明授权

US09030870B2 Threshold voltage compensation in a multilevel memory 有权
标题翻译：多电平存储器中的阈值电压补偿
公开(公告)号：US09030870B2
公开(公告)日：2015-05-12
申请号：US13219439
申请日：2011-08-26
申请人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
发明人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC分类号： G11C11/34 , G11C16/04 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

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