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1. 发明申请

US20130238958A1 APPARATUSES AND METHODS INCLUDING ERROR CORRECTION CODE ORGANIZATION 有权
公开(公告)号：US20130238958A1
公开(公告)日：2013-09-12
申请号：US13413363
申请日：2012-03-06
申请人： William Henry Radke
发明人： William Henry Radke
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1068 , G06F11/1016 , G06F11/1048 , G06F11/1072 , G11C29/52 , H03M13/116 , H03M13/2906 , H03M13/356
摘要： Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.

2. 发明申请

US20130051141A1 THRESHOLD VOLTAGE COMPENSATION IN A MULTILEVEL MEMORY 有权
标题翻译：多电平存储器中的阈值电压补偿
公开(公告)号：US20130051141A1
公开(公告)日：2013-02-28
申请号：US13219439
申请日：2011-08-26
申请人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
发明人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC分类号： G11C16/04
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。对于相邻编程的侵略存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

3. 发明授权

US08359514B2 Data and error correction code mixing device and method 有权
公开(公告)号：US08359514B2
公开(公告)日：2013-01-22
申请号：US12192426
申请日：2008-08-15
申请人： William Henry Radke
发明人： William Henry Radke
IPC分类号： H03M13/00
CPC分类号： H03M13/05 , G06F11/1008 , G06F11/1012 , G06F11/1072 , G11C29/00
摘要： Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.

4. 发明申请

US20110280080A1 MEMORY WITH MULTI-PAGE READ 有权
标题翻译：多页阅读记忆
公开(公告)号：US20110280080A1
公开(公告)日：2011-11-17
申请号：US13189726
申请日：2011-07-25
申请人： William Henry Radke
发明人： William Henry Radke
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/1021 , G11C16/04 , G11C16/3418 , G11C29/025 , G11C29/44 , G11C29/50
摘要： A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.
摘要翻译：描述了一种存储器件，其提供增加的输出数据以帮助在读取操作期间从位线耦合和浮动栅极耦合评估数据错误。读取多行或多页数据以允许内部或外部解码器评估存储器单元数据。

5. 发明授权

US07990763B2 Memory with weighted multi-page read 有权
标题翻译：内存加权多页阅读
公开(公告)号：US07990763B2
公开(公告)日：2011-08-02
申请号：US12267308
申请日：2008-11-07
申请人： William Henry Radke
发明人： William Henry Radke
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C7/1021 , G11C16/04 , G11C16/3418 , G11C29/025 , G11C29/44 , G11C29/50
摘要： A memory device provides increased output data to help evaluate data errors arising from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.
摘要翻译：存储器件提供增加的输出数据以帮助评估在读取操作期间由位线耦合和浮动栅极耦合引起的数据错误。读取多行或多页数据以允许内部或外部解码器评估存储器单元数据。

6. 发明申请

US20110093766A1 PROGRAMMING MANAGEMENT DATA FOR A MEMORY 有权
标题翻译：存储器的编程管理数据
公开(公告)号：US20110093766A1
公开(公告)日：2011-04-21
申请号：US12976712
申请日：2010-12-22
申请人： Michael Murray , William Henry Radke
发明人： Michael Murray , William Henry Radke
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1008 , G06F11/1072 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C29/00 , G11C2211/5642
摘要： Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additionally, various methods, apparatus, systems, and data structures may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.
摘要翻译：方法，装置，系统和数据结构可以操作以将块管理数据与数据的一部分组合，以产生组合部分的纠错数据，并存储数据，块管理数据，组合的纠错数据部分和用于存储器中的数据的纠错数据。方法，装置，系统和数据结构可以操作以生成或存储除了页面中的特定扇区之外的页面的多个扇区中的每一个的纠错数据，并且将块管理数据与特定扇区组合以生成修改的扇区。此外，各种方法，装置，系统和数据结构可以操作以产生或存储修改的扇区的纠错数据，并组合多个扇区，除了特定页面之外的多个扇区中的每一个的纠错数据，以及块管理数据和修改扇区的纠错数据。

7. 发明申请

US20100238726A1 FLASH MEMORY WITH MULTI-BIT READ 有权
标题翻译：具有多位读取的闪存
公开(公告)号：US20100238726A1
公开(公告)日：2010-09-23
申请号：US12790556
申请日：2010-05-28
申请人： William Henry Radke
发明人： William Henry Radke
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C8/10 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C29/00
摘要： A memory device is described that comprises determining which read data state of more than 2X read data states a memory cell is in after the memory cell has been programmed to one of 2X program data states, wherein the determined read data state corresponds to X digits of read data and at least one digit of error data, and wherein X is a positive integer.
摘要翻译：描述了一种存储器件，其包括在存储器单元已被编程为2X程序数据状态之一后确定存储单元处于多于2X读取数据状态的哪个读取数据状态，其中所确定的读取数据状态对应于读取数据和至少一个数字的错误数据，其中X是正整数。

8. 发明申请

US20090067249A1 MEMORY WITH MULTI-PAGE READ 有权
标题翻译：多页阅读记忆
公开(公告)号：US20090067249A1
公开(公告)日：2009-03-12
申请号：US12267308
申请日：2008-11-07
申请人： William Henry Radke
发明人： William Henry Radke
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C7/1021 , G11C16/04 , G11C16/3418 , G11C29/025 , G11C29/44 , G11C29/50
摘要： A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.
摘要翻译：描述了一种存储器件，其提供增加的输出数据以帮助在读取操作期间从位线耦合和浮动栅极耦合评估数据错误。读取多行或多页数据以允许内部或外部解码器评估存储器单元数据。

9. 发明授权

US09030870B2 Threshold voltage compensation in a multilevel memory 有权
标题翻译：多电平存储器中的阈值电压补偿
公开(公告)号：US09030870B2
公开(公告)日：2015-05-12
申请号：US13219439
申请日：2011-08-26
申请人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
发明人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC分类号： G11C11/34 , G11C16/04 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

10. 发明授权

US08560735B2 Chained bus method and device 有权
标题翻译：链式总线方法和装置
公开(公告)号：US08560735B2
公开(公告)日：2013-10-15
申请号：US12192450
申请日：2008-08-15
申请人： Victor Tsai , William Henry Radke , Bob Leibowitz
发明人： Victor Tsai , William Henry Radke , Bob Leibowitz
IPC分类号： G06F3/00
CPC分类号： G06F12/1081 , G06F3/007 , G06F11/3034 , G06F13/16 , G06F13/28 , G06F13/4063 , G06F13/4208 , G06F13/4234
摘要： Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.
摘要翻译：描述和示出了能够在链中配置的存储器件和方法。在一个配置中，主机使用单个数据输入端口和单个数据输出端口与存储器设备链路进行通信。描述了将标识符分配给链中的存储器件的方法，其包括检测下游存储器件的存在或不存在。在所选择的示例中，标识符被顺序地分配给链中的存储设备，直到没有检测到附加的下游存储器设备。

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