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1. 发明授权

US06064074A Semiconductor cathode and electron tube comprising a semiconductor cathode 失效
标题翻译：包括半导体阴极的半导体阴极和电子管
公开(公告)号：US06064074A
公开(公告)日：2000-05-16
申请号：US46035
申请日：1998-03-23
申请人： Tom Van Zutphen , Frederik C. Gehring , Mark A. De Samber , Erwin A. Hijzen , Ron Kroon
发明人： Tom Van Zutphen , Frederik C. Gehring , Mark A. De Samber , Erwin A. Hijzen , Ron Kroon
IPC分类号： H01J1/30 , H01J1/308 , H01J29/04 , H01L29/866 , H01L29/06
CPC分类号： H01J29/04 , H01J1/308
摘要： Semiconductor device with a semiconductor cathode having an emissive part (pn junction) separated from a contact part which has locations at which a controlled breakdown occurs on a contact part metallization at excessive voltages, so that, during manufacture and operation, the emissive part in an election tube is protected from damage.
摘要翻译：具有半导体阴极的半导体器件具有与接触部分分离的发射部分（pn结），所述接触部分具有在过电压下在接触部分金属化处发生受控击穿的位置，使得在制造和操作期间，发射部分在选管保护免受损坏。

2. 发明授权

US06198210B1 Electron tube having a semiconductor cathode with lower and higher bandgap layers 失效
标题翻译：电子管具有具有较低和较高带隙层的半导体阴极
公开(公告)号：US06198210B1
公开(公告)日：2001-03-06
申请号：US09198927
申请日：1998-11-24
申请人： Ron Kroon , Tom Van Zutphen , Erwin A. Hijzen
发明人： Ron Kroon , Tom Van Zutphen , Erwin A. Hijzen
IPC分类号： H01J2900
CPC分类号： H01J1/308 , H01J29/16
摘要： A semiconductor cathode (11) in a semiconductor structure, in which the sturdiness of the cathode is increased by covering the emitting surface (4) with a layer of a semiconductor material (7) having a larger bandgap than the semiconductor material of the semiconductor cathode. Various measures for increasing the electron-mission efficiency are indicated.
摘要翻译：一种半导体结构中的半导体阴极（11），其中通过用具有比半导体阴极的半导体材料更大的带隙的半导体材料（7）覆盖发光表面（4）来增加阴极的坚固性。指出了增加电子任务效率的各种措施。

3. 发明授权

US07629647B2 Trench MOS structure 有权
标题翻译：沟槽MOS结构
公开(公告)号：US07629647B2
公开(公告)日：2009-12-08
申请号：US10562254
申请日：2004-06-10
申请人： Raymond J. E. Hueting , Erwin A. Hijzen
发明人： Raymond J. E. Hueting , Erwin A. Hijzen
IPC分类号： H01L29/423
CPC分类号： H01L27/088 , H01L29/0692 , H01L29/1083 , H01L29/1087 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/78 , H01L29/7834 , H01L29/785
摘要： A semiconductor device has a trench (42) adjacent to a cell (18). The cell includes source and drain contact regions (26, 28), and a central body (40) of opposite conductivity type. The device is bidirectional and controls current in either direction with a relatively low on-resistance. Preferred embodiments include potential plates (60) that act together with source and drain drift regions (30, 32) to create a RESURF effect.
摘要翻译：半导体器件具有与电池（18）相邻的沟槽（42）。电池包括源极和漏极接触区域（26,28）以及具有相反导电类型的中心体（40）。器件是双向的，并且以相对较低的导通电阻来控制任一方向上的电流。优选实施例包括与源极和漏极漂移区（30,32）一起作用以产生RESURF效应的电位板（60）。

4. 发明授权

US07394144B2 Trench semiconductor device and method of manufacturing it 有权
标题翻译：沟槽半导体器件及其制造方法
公开(公告)号：US07394144B2
公开(公告)日：2008-07-01
申请号：US10594487
申请日：2005-03-29
申请人： Christelle Rochefort , Erwin A. Hijzen , Philippe Meunier-Beillard
发明人： Christelle Rochefort , Erwin A. Hijzen , Philippe Meunier-Beillard
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336 , H01L21/764
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66712 , H01L29/7811
摘要： Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls and base of the trenches followed by an overetching step to remove the trench insulating layer from the base of the trenches as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench and the base of the trenches. Silicon is selectively grown plugging the trenches with silicon plug (18) leaving void.
摘要翻译：与示例性实施例一致，制造了在漏极区域上具有漂移区域的减小的表面场效应型（RESURF）半导体器件。通过面罩中的开口形成沟槽。沟槽绝缘层沉积在沟槽的侧壁和基底上，随后进行过蚀刻步骤以从沟槽的底部除去沟槽绝缘层以及与第一主表面相邻的沟槽的侧壁的顶部，留下暴露的在沟槽的侧壁的顶部和沟槽的底部的硅。硅被选择性地生长，用硅塞（18）堵塞沟槽，留下空隙。

5. 发明授权

US06620669B2 Manufacture of trench-gate semiconductor devices 失效
公开(公告)号：US06620669B2
公开(公告)日：2003-09-16
申请号：US10152208
申请日：2002-05-21
申请人： Erwin A. Hijzen , Michael A. A. in't Zandt
发明人： Erwin A. Hijzen , Michael A. A. in't Zandt
IPC分类号： H01L218238
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/66348 , H01L29/7811
摘要： A vertical power transistor trench-gate semiconductor device has an active area (100) accommodating transistor cells and an inactive area (200) accommodating a gate electrode (25) (FIG. 6). While an n-type layer (14) suitable for drain regions still extends to the semiconductor body surface (10a), gate material (11) is deposited in silicon dioxide insulated (17) trenches (20) and planarised to the top of the trenches (20) in the active (100) and inactive (200) areas. Implantation steps then provide p-type channel-accommodating body regions (15A) in the active area (100) and p-type regions (15B) in the inactive area (200), and then source regions (13) in the active area (100). Further gate material (111) is then provided extending from the gate material (11) in the inactive area (200) and onto a top surface insulating layer (17B) for contact with the gate electrode (25). The channel profiles of the device are optimised by providing the p-type regions (15A) after the trench insulation (17), and voltage breakdown at the bottom corners of the trenches (20) is suppressed by providing the p-type regions (15B) in the inactive area (200).

6. 发明授权

US07485534B2 Method of manufacture of a trench-gate semiconductor device 有权
标题翻译：沟槽栅极半导体器件的制造方法
公开(公告)号：US07485534B2
公开(公告)日：2009-02-03
申请号：US10538217
申请日：2003-12-08
申请人： Erwin A. Hijzen
发明人： Erwin A. Hijzen
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368
摘要： A method of making a trench MOSFET includes forming a layer of porous silicon (26) at the bottom of a trench and then oxidizing the layer of porous silicon (26) to form a plug (30) at the bottom of the trench. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.
摘要翻译：制造沟槽MOSFET的方法包括在沟槽的底部形成多孔硅层（26），然后氧化多孔硅层（26），以在沟槽的底部形成插塞（30）。这在沟槽的底部形成厚的氧化物塞，从而减小栅极和漏极之间的电容。

7. 发明授权

US07160793B2 Edge termination in MOS transistors 失效
标题翻译： MOS晶体管的边缘端接
公开(公告)号：US07160793B2
公开(公告)日：2007-01-09
申请号：US11066408
申请日：2005-02-25
申请人： Raymond J. E. Hueting , Erwin A. Hijzen , Michael A. A. In't Zandt
发明人： Raymond J. E. Hueting , Erwin A. Hijzen , Michael A. A. In't Zandt
IPC分类号： H01L21/47
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7397 , H01L29/7811
摘要： A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g. a concentric annular device geometry, which may be circular or rectangular or ellipsoidal, in the active area and in the edge termination, or a device array of such concentric hexagonal or circular stripe cells, or a device array of square active cells with stripe edge cells, or a device array of hexagonal active cells with an edge termination of hexagonal edge cells.
摘要翻译： RESURF沟槽栅极MOSFET具有足够小的间距（相邻沟槽的紧密间隔），漏极漂移区的中间区域在MOSFET的阻塞状态下耗尽。然而，在已知的器件结构中，在有源器件区域的周边/边缘处和/或与栅极接合焊盘相邻处，仍然会发生过早击穿。为了防止过早击穿，本发明采用两个原则：栅极接合板或者连接到由有源单元包围的底层条纹沟槽网络，或者直接位于有源单元的顶部，并且在RESURF周围提供兼容的2D边缘终端方案有源设备区域。这些原理可以在各种蜂窝布局中实现，例如。在活动区域和边缘终止中可以是圆形或矩形或椭圆形的同心环形装置几何形状，或者这种同心六边形或圆形条纹细胞的装置阵列，或具有条纹边缘细胞的方形活性细胞的装置阵列，或具有六边形边缘单元的边缘终止的六边形活性单元的器件阵列。

8. 发明授权

US06780714B2 Semiconductor devices and their manufacture 有权
标题翻译：半导体器件及其制造
公开(公告)号：US06780714B2
公开(公告)日：2004-08-24
申请号：US10227672
申请日：2002-08-26
申请人： Mark A. Gajda , Michael A. A. in 't Zandt , Erwin A. Hijzen
发明人： Mark A. Gajda , Michael A. A. in 't Zandt , Erwin A. Hijzen
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4238 , H01L29/7811
摘要： In a cellular power MOSFET or other semiconductor device, a wide connection across the perimeter of an active device area (120) is replaced with a plurality of narrower conducting fingers (111). The fingers (11) are used as follows in providing a doped edge region (15a) that is required below the connection (110). Dopant (150,151) is implanted at spaces (112) between and beside the fingers (111) and is diffused to form a single continuous region (15a) extending beneath the fingers (111) and at the spaces (112) therebetween. This doped edge region (15a) may be, for example, a deep guard ring in an edge termination of a power MOSFET, or an extension of its channel-accommodating region (15). A trench-gate network (11) of the MOSFET can be connected by the conducting fingers to a gate bond pad and/or field plate (114).
摘要翻译：在蜂窝功率MOSFET或其它半导体器件中，穿过有源器件区域（120）的周边的宽连接被多个较窄的导电指状物（111）代替。在提供在连接（110）下方所需的掺杂边缘区域（15a）的情况下，如下使用指状物（11）。掺杂剂（150,151）注入在指状物（111）之间和旁边的空间（112）处，并且被扩散以形成在指状物（111）下方和其间的空间（112）处延伸的单个连续区域（15a）。该掺杂边缘区域（15a）可以是例如功率MOSFET的边缘终端中的深保护环或其沟道容纳区域（15）的延伸部。 MOSFET的沟槽栅极网络（11）可以通过导电指连接到栅极接合焊盘和/或场板（114）。

9. 发明授权

US06518129B2 Manufacture of trench-gate semiconductor devices 失效
公开(公告)号：US06518129B2
公开(公告)日：2003-02-11
申请号：US09932073
申请日：2001-08-17
申请人： Raymond J. E. Hueting , Erwin A. Hijzen , Michael A. A. Zand In't
发明人： Raymond J. E. Hueting , Erwin A. Hijzen , Michael A. A. Zand In't
IPC分类号： H01L21336
CPC分类号： H01L29/66348 , H01L27/10841 , H01L27/10876 , H01L29/66666 , H01L29/66848
摘要： The manufacture of a trench-gate semiconductor device, for example a power transistor or a memory device includes the steps of forming at a surface (10a) of a semiconductor body (10) a first mask (51) having a first window (51a), providing a thin layer of a second material (52) in the first window (51a), forming an intermediate mask (53A, 53B) of a third material having curved sidewalls and using the intermediate mask (53A, 53B) to form two L-shaped parts (52A, 52D and 52B, 52E) of the second material with a second window (52a) which is used to etch a trench-gate trench (20). The rectangular base portion (52D, 52E) of each L-shaped part ensures that the trench (20) is maintained narrow during etching. Narrow trenches are advantageous for low specific on-resistance and low RC delay in low voltage cellular trench-gate power transistors. Narrow deep trenches are also advantageous for cell density in DRAM devices where a memory cell has a switching transistor cell surrounded by a trench-gate and a storage capacitor in a lower part of the same trench.

10. 发明授权

US06359308B1 Cellular trench-gate field-effect transistors 有权
标题翻译：蜂窝沟槽栅场效应晶体管
公开(公告)号：US06359308B1
公开(公告)日：2002-03-19
申请号：US09624481
申请日：2000-07-24
申请人： Erwin A. Hijzen , Raymond J.E. Hueting
发明人： Erwin A. Hijzen , Raymond J.E. Hueting
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0661 , H01L29/407 , H01L29/41741 , H01L29/42368 , H01L29/66734 , H01L29/7808 , H01L29/7811
摘要： A cellular trench-gate field-effect transistor comprises a field plate (38) on dielectric material (28) in a perimeter trench (18). The dielectric material (28) forms a thicker dielectric layer than the gate dielectric layer (21) in the array trenches (11). The field plate (38) is connected to the source (3) or trench-gate (31) of the transistor and acts inwardly towards the cellular array rather than outwardly towards the body perimeter (15) because of its presence on the inside wall 18a of the trench (18) without acting on any outside wall (18b). The array and perimeter trenches (11,18) are sufficiently closely spaced, and the intermediate areas (4a, 4b) of the drain drift region (4) are sufficiently lowly doped, that the depletion layer (40) formed in the drain drift region (4) in the blocking state of the transistor depletes the whole of these intermediate areas between neighbouring trenches at a voltage less than the breakdown voltage. This arrangement reduces the risk of premature breakdown that can occur at high field points in the depletion layer (40), especially at the perimeter of the cellular array.
摘要翻译：蜂窝状沟槽栅极场效应晶体管包括在周边沟槽（18）中的电介质材料（28）上的场板（38）。电介质材料（28）形成比阵列沟槽（11）中的栅介质层（21）更厚的电介质层。场板（38）连接到晶体管的源极（3）或沟槽栅极（31）并且向内朝向蜂窝阵列作用，而不是向外朝向主体周边（15），因为其存在于内壁18a上的沟槽（18），而不作用在任何外壁（18b）上。阵列和周边沟槽（11,18）足够紧密地间隔开，并且漏极漂移区域（4）的中间区域（4a，4b）被充分地低掺杂，在漏极漂移区域中形成的耗尽层（40）（4）在晶体管的截止状态下，以小于击穿电压的电压消耗相邻沟槽之间的这些中间区域的全部。这种布置降低了可能在耗尽层（40）中的高场点发生的过早击穿的风险，特别是在蜂窝阵列的周边。

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