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1. 发明授权

US08681535B2 Nonvolatile latch circuit 失效
标题翻译：非易失性锁存电路
公开(公告)号：US08681535B2
公开(公告)日：2014-03-25
申请号：US13475332
申请日：2012-05-18
申请人： Alexander Mikhailovich Shukh , Tom A. Agan
发明人： Alexander Mikhailovich Shukh , Tom A. Agan
IPC分类号： G11C11/41
CPC分类号： G11C14/0081
摘要： A nonvolatile latch circuit that includes a logic circuitry comprising at least an input terminal, a clock terminal, an output terminal, and a nonvolatile memory element. The logic circuitry is electrically coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal. The nonvolatile memory element is electrically coupled to the output terminal at a first end and to a intermediate voltage source at a second end. A logic state of the latch circuit responds to an input signal during an active period of a clock signal. A logic state of the nonvolatile memory element is controlled by a bidirectional current running between the first and second ends. An electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source.
摘要翻译：一种非易失性锁存电路，其包括至少包括输入端子，时钟端子，输出端子和非易失性存储器元件的逻辑电路。逻辑电路在第一源极处电耦合到高电压源，并在第二源极处电耦合到低电压源。非易失性存储元件在第一端电耦合到输出端子，并在第二端电耦合到中间电压源。在时钟信号的有效时段期间，锁存电路的逻辑状态响应输入信号。非易失性存储元件的逻辑状态由在第一和第二端之间运行的双向电流来控制。中间电压源的电位高于低压源的电位，但低于高电压源的电位。

2. 发明申请

US20120306536A1 Nonvolatile Full Adder Circuit 有权
标题翻译：非易失性全加电路
公开(公告)号：US20120306536A1
公开(公告)日：2012-12-06
申请号：US13483452
申请日：2012-05-30
申请人： Alexander Mikhailovich Shukh , Tom A. Agan
发明人： Alexander Mikhailovich Shukh , Tom A. Agan
IPC分类号： H03K19/21
CPC分类号： H03K19/215 , H03K19/16
摘要： A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.
摘要翻译：一种非易失性全加器电路，包括全加器电路，其包括用于接收两个输入和进位信号的三个输入端，和输出端和进位输出端; 第一和第二非易失性存储元件分别电耦合到第一和第二输出端，并在其第二端处耦合到中间电压源。非易失性存储元件包括两个稳定的逻辑状态。每个非易失性存储器元件的逻辑状态由在其第一和第二端之间运行的双向电流来控制。全加器电路在其第一源极处电耦合到高电压源，并在其第二源极处耦合到低电压源，其中中间电压源的电位低于高压源的电位，但高于低压源的。

3. 发明申请

US20120257449A1 High Density Magnetic Random Access Memory 审中-公开
标题翻译：高密度磁性随机存取存储器
公开(公告)号：US20120257449A1
公开(公告)日：2012-10-11
申请号：US13441841
申请日：2012-04-07
申请人： Tom A. Agan , Alexander Mikhailovich Shukh
发明人： Tom A. Agan , Alexander Mikhailovich Shukh
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/16 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device that comprises a substrate, a memory cell including a magnetic tunnel junction which comprises a free ferromagnetic layer having a reversible magnetization direction directed perpendicular to the substrate, a pinned ferromagnetic layer having a fixed magnetization direction directed perpendicular to the substrate, and an insulating tunnel barrier layer disposed between the pinned and free layers, a first electrical circuit for applying a first current to a first conductor electrically coupled to the free layer to produce a bias magnetic field along a hard axis of the free layer, a second electrical circuit for applying a second current to a second conductor electrically coupled to the pinned layer to cause a spin momentum transfer in the free layer, wherein magnitudes of the bias magnetic field and spin momentum transfer in combination exceed a threshold and thus reverse the magnetization direction of the free layer.
摘要翻译：一种磁存储器件，包括衬底，包括磁性隧道结的存储单元，其包括具有垂直于衬底的可逆磁化方向的自由铁磁层，具有垂直于衬底的固定磁化方向的钉扎铁磁层，以及设置在被钉扎层和自由层之间的绝缘隧道势垒层，第一电路，用于将第一电流施加到电耦合到自由层的第一导体，以沿自由层的硬轴产生偏置磁场;第二电气电路，用于将第二电流施加到电耦合到被钉扎层的第二导体，以引起自由层中的自旋动量传递，其中组合的偏置磁场和自旋动量传递的大小超过阈值，并因此使磁化方向反转自由层。

4. 发明授权

US08976577B2 High density magnetic random access memory 有权
标题翻译：高密度磁随机存取存储器
公开(公告)号：US08976577B2
公开(公告)日：2015-03-10
申请号：US13554467
申请日：2012-07-20
申请人： Tom A. Agan , Alexander Mikhailovich Shukh
发明人： Tom A. Agan , Alexander Mikhailovich Shukh
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/161 , G11C11/1675 , Y10S977/933 , Y10S977/935
摘要： One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown.
摘要翻译：磁存储器件的一个实施例包括衬底和堆叠在衬底上的多个平面存储器阵列，每个存储器阵列包括多个平行的第一导电线，每个第一导线包括铁磁包层，多个平行的第二导线在多个交叉区域中重叠第一导线，每个磁性隧道结具有可控电阻的多个磁性隧道结，设置在交叉区域处，并在其第一端电耦合到第一导线之一，到其第二端的第二导线之一。磁隧道结的电阻通过在第一和第二端之间运行的自旋极化电流和与所述每个磁性隧道结同时施加的偏置磁场的联合效应来控制。描述和示出了其他实施例。

5. 发明授权

US09070456B2 High density magnetic random access memory 有权
标题翻译：高密度磁随机存取存储器
公开(公告)号：US09070456B2
公开(公告)日：2015-06-30
申请号：US13441841
申请日：2012-04-07
申请人： Tom A. Agan , Alexander Mikhailovich Shukh
发明人： Tom A. Agan , Alexander Mikhailovich Shukh
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/161 , G11C11/16 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device that comprises a substrate, a memory cell including a magnetic tunnel junction which comprises a free ferromagnetic layer having a reversible magnetization direction directed perpendicular to the substrate, a pinned ferromagnetic layer having a fixed magnetization direction directed perpendicular to the substrate, and an insulating tunnel barrier layer disposed between the pinned and free layers, a first electrical circuit for applying a first current to a first conductor electrically coupled to the free layer to produce a bias magnetic field along a hard axis of the free layer, a second electrical circuit for applying a second current to a second conductor electrically coupled to the pinned layer to cause a spin momentum transfer in the free layer, wherein magnitudes of the bias magnetic field and spin momentum transfer in combination exceed a threshold and thus reverse the magnetization direction of the free layer.
摘要翻译：一种磁存储器件，包括衬底，包括磁性隧道结的存储单元，其包括具有垂直于衬底的可逆磁化方向的自由铁磁层，具有垂直于衬底的固定磁化方向的钉扎铁磁层，以及设置在被钉扎层和自由层之间的绝缘隧道势垒层，第一电路，用于将第一电流施加到电耦合到自由层的第一导体，以沿自由层的硬轴产生偏置磁场;第二电气电路，用于将第二电流施加到电耦合到被钉扎层的第二导体，以引起自由层中的自旋动量传递，其中组合的偏置磁场和自旋动量传递的大小超过阈值，并因此使磁化方向反转自由层。

6. 发明授权

US08405421B2 Nonvolatile full adder circuit 有权
标题翻译：非易失性全加器电路
公开(公告)号：US08405421B2
公开(公告)日：2013-03-26
申请号：US13483452
申请日：2012-05-30
申请人： Alexander Mikhailovich Shukh , Tom A. Agan
发明人： Alexander Mikhailovich Shukh , Tom A. Agan
IPC分类号： G06F7/50
CPC分类号： H03K19/215 , H03K19/16
摘要： A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.
摘要翻译：一种非易失性全加器电路，包括全加器电路，其包括用于接收两个输入和进位信号的三个输入端，和输出端和进位输出端; 第一和第二非易失性存储元件分别电耦合到第一和第二输出端，并在其第二端处耦合到中间电压源。非易失性存储元件包括两个稳定的逻辑状态。每个非易失性存储器元件的逻辑状态由在其第一和第二端之间运行的双向电流来控制。全加器电路在其第一源极处电耦合到高电压源，并在其第二源极处耦合到低电压源，其中中间电压源的电位低于高压源的电位，但高于低压源的。

7. 发明申请

US20120307549A1 Nonvolatile Latch Circuit 失效
标题翻译：非易失性锁存电路
公开(公告)号：US20120307549A1
公开(公告)日：2012-12-06
申请号：US13475332
申请日：2012-05-18
申请人： Alexander Mikhailovich Shukh , Tom A. Agan
发明人： Alexander Mikhailovich Shukh , Tom A. Agan
IPC分类号： G11C11/41
CPC分类号： G11C14/0081
摘要： A nonvolatile latch circuit that includes a logic circuitry comprising at least an input terminal, a clock terminal, an output terminal, and a nonvolatile memory element. The logic circuitry is electrically coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal. The nonvolatile memory element is electrically coupled to the output terminal at a first end and to a intermediate voltage source at a second end. A logic state of the latch circuit responds to an input signal during an active period of a clock signal. A logic state of the nonvolatile memory element is controlled by a bidirectional current running between the first and second ends. An electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source.
摘要翻译：一种非易失性锁存电路，其包括至少包括输入端子，时钟端子，输出端子和非易失性存储器元件的逻辑电路。逻辑电路在第一源极处电耦合到高电压源，并在第二源极处电耦合到低电压源。非易失性存储元件在第一端电耦合到输出端子，并在第二端电耦合到中间电压源。在时钟信号的有效时段期间，锁存电路的逻辑状态响应输入信号。非易失性存储元件的逻辑状态由在第一和第二端之间运行的双向电流来控制。中间电压源的电位高于低压源的电位，但低于高电压源的电位。

8. 发明申请

US20120281465A1 High Density Magnetic Random Access Memory 审中-公开
标题翻译：高密度磁性随机存取存储器
公开(公告)号：US20120281465A1
公开(公告)日：2012-11-08
申请号：US13554467
申请日：2012-07-20
申请人： Tom A. Agan , Alexander Mikhailovich Shukh
发明人： Tom A. Agan , Alexander Mikhailovich Shukh
IPC分类号： G11C11/00
CPC分类号： G11C11/161 , G11C11/1675 , Y10S977/933 , Y10S977/935
摘要： One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown.
摘要翻译：磁存储器件的一个实施例包括衬底和堆叠在衬底上的多个平面存储器阵列，每个存储器阵列包括多个平行的第一导电线，每个第一导线包括铁磁包层，多个平行的第二导线在多个交叉区域中重叠第一导线，每个磁性隧道结具有可控电阻的多个磁性隧道结，设置在交叉区域处，并在其第一端电耦合到第一导线之一，到其第二端的第二导线之一。磁隧道结的电阻通过在第一和第二端之间运行的自旋极化电流和与所述每个磁性隧道结同时施加的偏置磁场的联合效应来控制。描述和示出了其他实施例。

9. 发明申请

US20140252438A1 Three-Dimensional Magnetic Random Access Memory With High Speed Writing 审中-公开
标题翻译：具有高速写入的三维磁性随机存取存储器
公开(公告)号：US20140252438A1
公开(公告)日：2014-09-11
申请号：US13792157
申请日：2013-03-10
申请人： Alexander Mikhailovich Shukh
发明人： Alexander Mikhailovich Shukh
IPC分类号： H01L43/02
CPC分类号： H01L27/228 , G11C11/1675 , H01L43/08
摘要： One embodiment of a magnetic random access memory includes a magnetic memory cell comprising a transistor disposed on a substrate, electrically coupled to a first conductive line and comprising a gate width; a plurality of magnetoresistive elements, each magnetoresistive element comprising an element width, a pinned magnetic layer comprising a fixed magnetization direction directed perpendicular to the substrate, a free magnetic layer comprising a reversible magnetization direction directed perpendicular to the substrate, and a tunnel barrier layer residing between the pinned and free layers; and a plurality of parallel second conductive lines overlapping the first conductive line. The plurality of the parallel second lines is independently electrically coupled to the plurality of magnetoresistive elements at first terminals, and the plurality of magnetoresistive elements is jointly electrically coupled to the transistor at second terminals, wherein the gate width is substantially larger than the element width. Other embodiments are described and shown.
摘要翻译：磁性随机存取存储器的一个实施例包括磁存储单元，其包括设置在基板上的晶体管，电耦合到第一导线并且包括栅极宽度; 多个磁阻元件，每个磁阻元件包括元件宽度，包括垂直于衬底的固定磁化方向的钉扎磁性层，包括垂直于衬底的可逆磁化方向的自由磁性层以及驻留在衬底上的隧道势垒层在钉扎层和自由层之间; 以及与第一导线重叠的多个平行的第二导线。多个平行的第二线路在第一端子处独立地电耦合到多个磁阻元件，并且多个磁阻元件在第二端子处共同电耦合到晶体管，其中栅极宽度基本上大于元件宽度。描述和示出了其他实施例。

10. 发明授权

US08773896B2 Nonvolatile latch circuit 有权
标题翻译：非易失性锁存电路
公开(公告)号：US08773896B2
公开(公告)日：2014-07-08
申请号：US13851937
申请日：2013-03-27
申请人： Alexander Mikhailovich Shukh
发明人： Alexander Mikhailovich Shukh
IPC分类号： G11C11/16 , G11C14/00
CPC分类号： G11C11/16 , G11C11/165 , G11C14/00 , G11C14/0081 , G11C14/009
摘要： One embodiment of a nonvolatile latch circuit comprises a latch circuitry configurated to temporarily hold data and comprising a first output terminal, the latch circuitry is coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal, and a first nonvolatile memory element configurated to store said data and comprising a low resistance and a high resistance. The first memory element is connected in-series with a first transistor and coupled between the first output terminal and an intermediate voltage source. The resistance of the first memory element is changed by a bidirectional current running between the first output terminal and the intermediate voltage source, wherein an electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source. Other embodiments are described and shown.
摘要翻译：非易失性锁存电路的一个实施例包括被配置为临时保存数据并且包括第一输出端子的锁存电路，锁存电路在第一源极端耦合到高电压源，在第二源极处耦合到低电压源，以及配置为存储所述数据并且包括低电阻和高电阻的第一非易失性存储器元件。第一存储元件与第一晶体管串联连接，并耦合在第一输出端和中间电压源之间。第一存储元件的电阻通过在第一输出端和中间电压源之间的双向电流而改变，其中中间电压源的电位高于低电压源的电位，但是低于高电压源的电位电压源。描述和示出了其他实施例。

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