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1. 发明申请

US20180187308A1 METHOD AND SYSTEM FOR SCULPTING SPACER SIDEWALL MASK 审中-公开
公开(公告)号：US20180187308A1
公开(公告)日：2018-07-05
申请号：US15906660
申请日：2018-02-27
申请人： Tokyo Electron Limited
发明人： Vinh Luong , Akiteru Ko
IPC分类号： C23C16/52 , C23C16/455 , H01L21/3213 , H01L21/311 , H01L21/033
CPC分类号： C23C16/52 , C23C16/45525 , H01L21/0337 , H01L21/31116 , H01L21/31122 , H01L21/32137 , H01L21/32139
摘要： Provided is a method of forming a spacer sidewall mask, the method comprising: providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer; performing a breakthrough etch process including growth of a conformal native silicon oxide layer, creating an ALD patterned structure; performing a spacer sidewall sculpting process on the ALD patterned structure; performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal; and performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a trapezoidal shape.

2. 发明授权

US09899219B2 Trimming inorganic resists with selected etchant gas mixture and modulation of operating variables 有权
公开(公告)号：US09899219B2
公开(公告)日：2018-02-20
申请号：US15232330
申请日：2016-08-09
申请人： Tokyo Electron Limited
发明人： Vinh Luong , Akiteru Ko
IPC分类号： H01L21/033 , H01L21/311 , H01L21/683 , H01L21/66 , H01L21/67
CPC分类号： H01L21/0337 , G03F7/0043 , G03F7/094 , G03F7/405 , H01J2237/3342 , H01L21/0332 , H01L21/31122 , H01L21/32139 , H01L21/67017 , H01L21/67109 , H01L21/6831 , H01L22/12 , H01L22/20 , H01L22/26
摘要： Provided is a method of trimming an inorganic resist in an integration scheme, the method comprising: disposing a substrate in a process chamber, the substrate having an inorganic resist layer and an underlying layer comprising an oxide layer, a silicon nitride layer, and a base layer, the inorganic resist layer having an inorganic structure pattern; performing an inorganic resist trimming process to selectively remove a portion of the inorganic resist structure pattern on the substrate, the trimming process using a first etchant gas mixture and generating a first pattern; controlling selected two or more operating variables of the integration scheme in order to achieve target integration objectives; wherein the first etchant gas mixture comprises a fluorine-containing gas and a diluent gas; and wherein the target integration objectives include a target critical dimension (CD), a target line edge roughness (LER), a target line width roughness (LWR) and a target substrate throughput.

3. 发明授权

US10672618B2 Systems and methods for patterning features in tantalum nitride (TaN) layer 审中-公开
公开(公告)号：US10672618B2
公开(公告)日：2020-06-02
申请号：US16032759
申请日：2018-07-11
申请人： Tokyo Electron Limited , International Business Machines Corporation
发明人： Vinh Luong , Isabel Cristina Chu , Ashim Dutta
IPC分类号： H01L21/3065 , H01L21/033 , H01L21/311 , H01L21/3213 , H01J37/32
摘要： Embodiments of systems and methods for patterning features in tantalum nitride (TaN) are described. In an embodiment, a method may include receiving a substrate comprising a TaN layer. The method may also include etching the substrate to expose at least a portion of the TaN layer. Additionally, the method may include performing a passivation process to reduce lateral etching of the TaN layer. The method may further include etching the TaN layer to form a feature therein, wherein the passivation process is controlled to meet one or more target passivation objectives.

4. 发明申请

US20170243744A1 Trimming Inorganic Resists With Selected Etchant Gas Mixture And Modulation of Operating Variables 有权
公开(公告)号：US20170243744A1
公开(公告)日：2017-08-24
申请号：US15232330
申请日：2016-08-09
申请人： Tokyo Electron Limited
发明人： Vinh Luong , Akiteru Ko
IPC分类号： H01L21/033 , H01L21/683 , H01L21/66 , H01L21/311
CPC分类号： H01L21/0337 , G03F7/0043 , G03F7/094 , G03F7/405 , H01J2237/3342 , H01L21/0332 , H01L21/31122 , H01L21/32139 , H01L21/67017 , H01L21/67109 , H01L21/6831 , H01L22/12 , H01L22/20 , H01L22/26
摘要： Provided is a method of trimming an inorganic resist in an integration scheme, the method comprising: disposing a substrate in a process chamber, the substrate having an inorganic resist layer and an underlying layer comprising an oxide layer, a silicon nitride layer, and a base layer, the inorganic resist layer having an inorganic structure pattern; performing an inorganic resist trimming process to selectively remove a portion of the inorganic resist structure pattern on the substrate, the trimming process using a first etchant gas mixture and generating a first pattern; controlling selected two or more operating variables of the integration scheme in order to achieve target integration objectives; wherein the first etchant gas mixture comprises a fluorine-containing gas and a diluent gas; and wherein the target integration objectives include a target critical dimension (CD), a target line edge roughness (LER), a target line width roughness (LWR) and a target substrate throughput.

5. 发明授权

US10260150B2 Method and system for sculpting spacer sidewall mask 有权
公开(公告)号：US10260150B2
公开(公告)日：2019-04-16
申请号：US15906660
申请日：2018-02-27
申请人： Tokyo Electron Limited
发明人： Vinh Luong , Akiteru Ko
IPC分类号： C23C16/52 , H01L21/32 , H01L21/033 , H01L21/311 , H01L21/3213 , C23C16/455
摘要： Provided is a method of forming a spacer sidewall mask, the method comprising: providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer; performing a breakthrough etch process including growth of a conformal native silicon oxide layer, creating an ALD patterned structure; performing a spacer sidewall sculpting process on the ALD patterned structure; performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal; and performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a trapezoidal shape.

6. 发明申请

US20170053793A1 METHOD AND SYSTEM FOR SCULPTING SPACER SIDEWALL MASK 审中-公开
标题翻译：用于分离间隔件面罩的方法和系统
公开(公告)号：US20170053793A1
公开(公告)日：2017-02-23
申请号：US15227096
申请日：2016-08-03
申请人： Tokyo Electron Limited
发明人： Vinh Luong , Akiteru Ko
IPC分类号： H01L21/02 , C23C16/52 , C23C16/455 , H01L21/306 , H01L21/311
CPC分类号： C23C16/52 , C23C16/45525 , H01L21/0337 , H01L21/31116 , H01L21/31122 , H01L21/32137 , H01L21/32139
摘要： Provided is a method of forming a spacer sidewall mask, the method comprising: providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer; performing a breakthrough etch process including growth of a conformal native silicon oxide layer, creating an ALD patterned structure; performing a spacer sidewall sculpting process on the ALD patterned structure; performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal; and performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a trapezoidal shape.
摘要翻译：提供一种形成间隔壁侧壁的方法，所述方法包括：在处理室中提供衬底，所述衬底具有碳心轴图案和下层，所述下层包括位于氮化硅层上方的非晶硅层; 执行突破蚀刻工艺，包括保形天然氧化硅层的生长，产生ALD图案化结构; 在ALD图案结构上执行间隔壁侧壁雕刻工艺; 在ALD图案化结构上进行非晶硅主蚀刻（ME）工艺，ME工艺引起间隔氧化物开放和碳芯棒去除; 以及在所述ALD间隔物氧化物图案上对蚀刻（OE）工艺执行无定形硅ME，所述ME OE工艺将所述ALD间隔物氧化物图案转移到所述非晶硅层中，产生包含具有梯形的第一雕刻子结构的第一雕刻图案形状。

7. 发明申请

US20190096672A1 Systems and Methods for Patterning Features in Tantalum Nitride (TaN) Layer 审中-公开
公开(公告)号：US20190096672A1
公开(公告)日：2019-03-28
申请号：US16032759
申请日：2018-07-11
申请人： Tokyo Electron Limited
发明人： Vinh Luong , Isabel Cristina Chu , Ashim Dutta
IPC分类号： H01L21/033
摘要： Embodiments of systems and methods for patterning features in tantalum nitride (TaN) are described. In an embodiment, a method may include receiving a substrate comprising a TaN layer. The method may also include etching the substrate to expose at least a portion of the TaN layer. Additionally, the method may include performing a passivation process to reduce lateral etching of the TaN layer. The method may further include etching the TaN layer to form a feature therein, wherein the passivation process is controlled to meet one or more target passivation objectives.

8. 发明授权

US09978563B2 Plasma treatment method to meet line edge roughness and other integration objectives 有权
公开(公告)号：US09978563B2
公开(公告)日：2018-05-22
申请号：US15266397
申请日：2016-09-15
申请人： Tokyo Electron Limited
发明人： Vinh Luong , Akiteru Ko
IPC分类号： H01L21/302 , H01J37/32 , H01L21/027 , H01L21/3105 , B81C1/00
CPC分类号： H01J37/32082 , B81C1/00531 , H01J37/32165 , H01J37/3244 , H01L21/0274 , H01L21/31058 , H01L21/31116
摘要： Provided is a method of patterning a layer on a substrate using an integration scheme, the method comprising: disposing a substrate having a structure pattern layer, a neutral layer, and an underlying layer, the structure pattern layer comprising a first material and a second material; performing a first treatment process using a first process gas mixture to form a first pattern, the first process gas comprising a mixture of CxHyFz and argon; performing a second treatment process using a second process gas mixture to form a second pattern, the second process gas comprising a mixture of low oxygen-containing gas and argon; concurrently controlling selected two or more operating variables of the integration scheme in order to achieve target integration objectives.

9. 发明申请

US20170213700A1 Plasma Treatment Method to Meet Line Edge Roughness and Other Integration Objectives 有权
公开(公告)号：US20170213700A1
公开(公告)日：2017-07-27
申请号：US15266397
申请日：2016-09-15
申请人： Tokyo Electron Limited
发明人： Vinh Luong , Akiteru Ko
IPC分类号： H01J37/32 , H01L21/027
CPC分类号： H01J37/32082 , B81C1/00531 , H01J37/32165 , H01J37/3244 , H01L21/0274 , H01L21/31058 , H01L21/31116
摘要： Provided is a method of patterning a layer on a substrate using an integration scheme, the method comprising: disposing a substrate having a structure pattern layer, a neutral layer, and an underlying layer, the structure pattern layer comprising a first material and a second material; performing a first treatment process using a first process gas mixture to form a first pattern, the first process gas comprising a mixture of CxHyFz and argon; performing a second treatment process using a second process gas mixture to form a second pattern, the second process gas comprising a mixture of low oxygen-containing gas and argon; concurrently controlling selected two or more operating variables of the integration scheme in order to achieve target integration objectives.

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