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1. 发明授权

US06459126B1 Semiconductor device including a MIS transistor 有权
标题翻译：包括MIS晶体管的半导体器件
公开(公告)号：US06459126B1
公开(公告)日：2002-10-01
申请号：US09852658
申请日：2001-05-11
申请人： Tohru Mogami , Mitsuhiro Togo , Koji Watanabe , Toyoji Yamamoto , Nobuyuki Ikarashi , Kazutoshi Shiba , Toru Tatsumi , Haruhiko Ono
发明人： Tohru Mogami , Mitsuhiro Togo , Koji Watanabe , Toyoji Yamamoto , Nobuyuki Ikarashi , Kazutoshi Shiba , Toru Tatsumi , Haruhiko Ono
IPC分类号： H01L2362
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/823462 , H01L29/513 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A MIS transistor has a gate insulating film made of silicon oxynitride and having a specific dielectric constant which is larger than the expected specific dielectric constant calculated based on a weighted average of the specific dielectric constants based on the weight ratio of the silicon oxide and the silicon nitride contained in the silicon oxynitride film. The gate insulating film having a smaller thickness prevents impurities in the overlying gate electrode from penetrating through the gate insulating film to degrade the silicon substrate.
摘要翻译： MIS晶体管具有由氮氧化硅制成的栅极绝缘膜，其具有比基于氧化硅和硅的重量比的基于特定介电常数的加权平均值计算的预期比介电常数的比介电常数包含在氮氧化硅膜中的氮化物。具有较小厚度的栅极绝缘膜防止上覆栅极电极中的杂质穿过栅极绝缘膜而劣化硅衬底。

2. 发明授权

US06933569B2 SOI MOSFET 失效
公开(公告)号：US06933569B2
公开(公告)日：2005-08-23
申请号：US10668349
申请日：2003-09-24
申请人： Risho Koh , Shigeharu Yamagami , Jong-wook Lee , Hitoshi Wakabayashi , Yukishige Saito , Atsushi Ogura , Mitsuru Narihiro , Kohichi Arai , Hisashi Takemura , Tohru Mogami , Toyoji Yamamoto , Yukinori Ochiai
发明人： Risho Koh , Shigeharu Yamagami , Jong-wook Lee , Hitoshi Wakabayashi , Yukishige Saito , Atsushi Ogura , Mitsuru Narihiro , Kohichi Arai , Hisashi Takemura , Tohru Mogami , Toyoji Yamamoto , Yukinori Ochiai
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L21/01
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/78609 , H01L29/78615 , H01L29/78621
摘要： A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.
摘要翻译：半导体器件包括形成在绝缘体上的半导体层，形成在半导体层上的栅极绝缘膜，形成在栅极绝缘膜上并沿第一方向延伸的栅电极，在两侧的半导体层中形成的源/漏区所述半导体层中的主体接触区域，其中比所述栅极绝缘膜更厚的场绝缘膜介于所述半导体层和所述栅电极的延伸部分之间的部分隔离区域，以及完全隔离区域去除绝缘体上的半导体层。完全隔离区域形成为与平行于源极/漏极区域的第一方向的一侧的至少一部分接触。

3. 发明授权

US08900973B2 Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion 有权
标题翻译：通过植入和热扩散使得FinFET结构中的压应变应变pFET通道的方法
公开(公告)号：US08900973B2
公开(公告)日：2014-12-02
申请号：US13221198
申请日：2011-08-30
申请人： Nathaniel C. Berliner , Pranita Kulkarni , Nicolas Loubet , Kingsuk Maitra , Sanjay C. Mehta , Paul A. Ronsheim , Toyoji Yamamoto , Zhengmao Zhu
发明人： Nathaniel C. Berliner , Pranita Kulkarni , Nicolas Loubet , Kingsuk Maitra , Sanjay C. Mehta , Paul A. Ronsheim , Toyoji Yamamoto , Zhengmao Zhu
IPC分类号： H01L21/326 , H01L21/84 , H01L27/12 , H01L29/78
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7848
摘要： A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
摘要翻译：制造半导体器件的方法在pFET区域中形成第一鳍，并且在nFET区域中形成第二鳍。包含应变材料的多个保形微层沉积在第一和第二鳍片上。在第一翅片上形成保护盖材料，并且从第二翅片选择性地去除保形层。然后将应变材料热扩散到第一鳍中。在热退火之后以及在从第二散热片选择性地去除保形微层之后，从第一散热片上去除保护帽材料。

4. 发明申请

US20130052801A1 METHOD TO ENABLE COMPRESSIVELY STRAINED PFET CHANNEL IN A FINFET STRUCTURE BY IMPLANT AND THERMAL DIFFUSION 有权
标题翻译：通过植入和热扩散在FinFET结构中实现压缩应变PFET通道的方法
公开(公告)号：US20130052801A1
公开(公告)日：2013-02-28
申请号：US13221198
申请日：2011-08-30
申请人： Nathaniel C. Berliner , Pranita Kulkarni , Nicolas Loubet , Kingsuk Maitra , Sanjay C. Mehta , Paul A. Ronsheim , Toyoji Yamamoto , Zhengmao Zhu
发明人： Nathaniel C. Berliner , Pranita Kulkarni , Nicolas Loubet , Kingsuk Maitra , Sanjay C. Mehta , Paul A. Ronsheim , Toyoji Yamamoto , Zhengmao Zhu
IPC分类号： H01L21/326
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7848
摘要： A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
摘要翻译：制造半导体器件的方法在pFET区域中形成第一鳍，并且在nFET区域中形成第二鳍。包含应变材料的多个保形微层沉积在第一和第二鳍片上。在第一翅片上形成保护盖材料，并且从第二翅片选择性地去除保形层。然后将应变材料热扩散到第一鳍中。在热退火之后以及在从第二散热片选择性地去除保形微层之后，从第一散热片上去除保护帽材料。

5. 发明授权

US4482245A Apparatus for measuring the color of a brilliant-cut diamond 失效
标题翻译：用于测量辉光切割钻石颜色的装置
公开(公告)号：US4482245A
公开(公告)日：1984-11-13
申请号：US444606
申请日：1982-11-26
申请人： Hideki Makabe , Toyoji Yamamoto , Yoshio Matsueda , Yasunori Ito , Katsuto Yamada
发明人： Hideki Makabe , Toyoji Yamamoto , Yoshio Matsueda , Yasunori Ito , Katsuto Yamada
IPC分类号： G01J3/50 , G01J3/04 , G01J3/46 , G01N21/87
CPC分类号： G01J3/46 , G01J3/0251 , G01J3/04 , G01J3/502 , G01N21/87 , G01J3/465 , G01N2201/065
摘要： An apparatus for measuring a diamond color comprises a light source composed of a lamp and an integrating sphere for diffusing light therein emitted from the lamp; a diamond holder including diamond supporting head means and suction base means, thereby positioning the table facet of the diamond in the integrating sphere for allowing the diffused light from the light source to fall on the table facet of the diamond; a monochromator for separating a beam of light as it emerges from the diamond through the table facet side into a spectrum; a photodetector for detecting the light from the monochromator; variable slit means disposed in at least one of the monochromator and the photodetector for adjusting the size of the beam of light to a diameter of the diamond; a measurement unit for controlling at least the monochromator to obtain a spectrum of the light which has passed through the diamond; and an arithmetic unit for deriving tristimulus values X, Y and Z from the spectrum of the light from the diamond; which is able to measure the colors of brilliant-cut diamonds easily and objectively.
摘要翻译：用于测量金刚石颜色的装置包括由灯组成的光源和用于从灯发射的光的积分球; 金刚石保持器，其包括金刚石支撑头装置和抽吸底座装置，从而将金刚石的台面定位在积分球中，以允许来自光源的漫射光落在金刚石的台面上; 单色仪，用于当光束从金刚石通过台面侧面分离成光谱时，分离光束; 用于检测来自单色仪的光的光电检测器; 设置在所述单色仪和所述光电检测器中的至少一个中的可变狭缝装置，用于将所述光束的尺寸调整为所述金刚石的直径; 测量单元，用于至少控制单色仪以获得穿过金刚石的光的光谱; 以及用于从来自金刚石的光的光谱导出三刺激值X，Y和Z的算术单元; 它能够轻松，客观地测量辉煌切割钻石的颜色。

6. 发明授权

US5770494A Process of fabricating semiconductor device having gate structure doped through diffusion from refractory metal silicide into polysilicon 失效
$Process of fabricating semiconductor device having gate structure doped through diffusion from refractory metal silicide into polysilicon$
标题翻译：制造具有通过从难熔金属硅化物扩散到多晶硅中而掺杂的栅极结构的半导体器件的工艺
公开(公告)号：US5770494A
公开(公告)日：1998-06-23
申请号：US617207
申请日：1996-03-18
申请人： Toyoji Yamamoto , Kiyoshi Takeuchi
发明人： Toyoji Yamamoto , Kiyoshi Takeuchi
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L21/8234 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66575 , H01L21/28061 , H01L21/8238
摘要： Using a lamination of a tungsten silicide layer and a non-doped polysilicon layer as a mask, a dopant impurity is ion implanted into a semiconductor substrate so as to form impurity regions and dope the tungsten silicide layer with the dopant impurity, and the dopant impurity is diffused from the tungsten silicide layer into the non-doped polysilicon layer during the activation of the dopant impurity introduced into the substrate, thereby making the process simple.
摘要翻译：使用硅化钨层和非掺杂多晶硅层的层叠作为掩模，将掺杂剂杂质离子注入到半导体衬底中，以形成杂质区域并掺杂掺杂剂杂质的硅化钨层，掺杂杂质在引入衬底的掺杂剂杂质的激活期间从硅化钨层扩散到非掺杂多晶硅层中，从而使得工艺简单。

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