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    • 7. 发明授权
    • Selective receiver for each processor in a multiple processor system
    • 多处理器系统中每个处理器的选择性接收器
    • US5313620A
    • 1994-05-17
    • US724194
    • 1991-07-01
    • David M. CohenBhaskarpillai GopinathJohn R. Vollaro
    • David M. CohenBhaskarpillai GopinathJohn R. Vollaro
    • G06F13/372G06F1/04
    • G06F13/372
    • Circuitry, and associated methodology in a parallel processing system for sharing the address space among a plurality of autonomous processors (110, 210, 310) communicating over a common bus (60) provides an efficient, non-destructive data transfer and storage environment. This is effected by augmenting each processor with a global clock (31), state alignment circuit (41, 42, 43) to synchronize the processors with the global clock buffers (140, 240, 340) for storing data received off the bus, and circuitry (130, 230, 330) for selectively enabling the buffer to accept those segments of data having addresses allocated to the given processor. To ensure that processing states are aligned, each state alignment circuit inhibits incrementing of the global clock until each corresponding processor transceives necessary data over the bus. To avoid overwriting of data during bus conflicts, the buffers are arranged to store data on a first-in, first-out basis and to control the processing states and data transfer in correspondence to respective bus and processor states.
    • 用于在通过公共总线(60)通信的多个自治处理器(110,210,310)中共享地址空间的并行处理系统中的电路和相关方法提供了一种有效的,非破坏性的数据传输和存储环境。 这通过用全局时钟(31),状态对准电路(41,42,43)来增强每个处理器来实现,以使处理器与全局时钟缓冲器(140,240,340)同步,用于存储从总线接收的数据,以及 电路(130,230,330),用于选择性地使所述缓冲器能够接受具有分配给给定处理器的地址的数据段。 为了确保处理状态对齐,每个状态对准电路禁止全局时钟的递增,直到每个对应的处理器通过总线收发必要的数据。 为了避免在总线冲突期间覆盖数据,缓冲器被布置成以先入先出的方式存储数据,并且根据相应的总线和处理器状态控制处理状态和数据传输。