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1. 发明授权

US5814893A Semiconductor device having a bond pad 失效
标题翻译：具有接合焊盘的半导体器件
公开(公告)号：US5814893A
公开(公告)日：1998-09-29
申请号：US799925
申请日：1997-02-13
申请人： Ting-Chen Hsu , Edward O. Travis , Clifford M. Howard , Stephen G. Jamison
发明人： Ting-Chen Hsu , Edward O. Travis , Clifford M. Howard , Stephen G. Jamison
IPC分类号： H01L21/20 , H01L21/316 , H01L21/318 , H01L21/60 , H01L23/485 , H01L23/532 , H01L23/48 , H01L23/52
CPC分类号： H01L24/48 , H01L21/2007 , H01L23/53223 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05187 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/4807 , H01L2224/48458 , H01L2224/4847 , H01L2224/48724 , H01L2224/48747 , H01L24/45 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , Y10S438/958
摘要： Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.
摘要翻译：形成接合焊盘（394,106）和接合焊盘开口（62,108），使得接合焊盘开口（62,108）与焊盘（394,106）的导电部分（398,106）不对称。如果接合焊盘更可能从接合焊盘（394,106）的划线侧提升，则形成接合焊盘开口（62,108），使得钝化层（52）覆盖导电部分 398,106）在划线（40）附近。如果接合焊盘（394,106）更可能从另一侧抬起，则钝化层（52）覆盖在导电部分（398,106）的另一侧的更多侧。除了降低起重风险外，还应降低污染问题。

2. 发明授权

US5661082A Process for forming a semiconductor device having a bond pad 失效
标题翻译：用于形成具有接合焊盘的半导体器件的工艺
公开(公告)号：US5661082A
公开(公告)日：1997-08-26
申请号：US376208
申请日：1995-01-20
申请人： Ting-Chen Hsu , Edward O. Travis , Clifford M. Howard , Stephen G. Jamison
发明人： Ting-Chen Hsu , Edward O. Travis , Clifford M. Howard , Stephen G. Jamison
IPC分类号： H01L21/20 , H01L21/316 , H01L21/318 , H01L21/60 , H01L23/485 , H01L23/532 , H01L21/44
CPC分类号： H01L24/48 , H01L21/2007 , H01L23/53223 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05187 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/4807 , H01L2224/48458 , H01L2224/4847 , H01L2224/48724 , H01L2224/48747 , H01L24/45 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , Y10S438/958
摘要： Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.
摘要翻译：形成接合焊盘（394,106）和接合焊盘开口（62,108），使得接合焊盘开口（62,108）与焊盘（394,106）的导电部分（398,106）不对称。如果接合焊盘更可能从接合焊盘（394,106）的划线侧提升，则形成接合焊盘开口（62,108），使得钝化层（52）覆盖导电部分 398,106）在划线（40）附近。如果接合焊盘（394,106）更可能从另一侧抬起，则钝化层（52）覆盖在导电部分（398,106）的另一侧的更多侧。除了降低起重风险外，还应降低污染问题。

3. 发明授权

US08575962B2 Integrated circuit having critical path voltage scaling and method therefor 有权
标题翻译：具有关键路径电压调节的集成电路及其方法
公开(公告)号：US08575962B2
公开(公告)日：2013-11-05
申请号：US13220302
申请日：2011-08-29
申请人： Jianan Yang , Stephen G. Jamison , David L. Medlock , Gary Waugh
发明人： Jianan Yang , Stephen G. Jamison , David L. Medlock , Gary Waugh
IPC分类号： H03K19/0175 , G06F17/50
CPC分类号： H03K3/356156
摘要： An integrated circuit comprises logic circuitry having a plurality of signal paths. A signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths. The signal path includes a plurality of components. The plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths.
摘要翻译：集成电路包括具有多个信号路径的逻辑电路。多个信号路径的信号路径具有大于多个信号路径中的任何其它信号路径的传播延迟的传播延迟。信号路径包括多个组件。多个组件被提供有比多个信号路径中的任何其它信号路径更高的电源电压。

4. 发明授权

US5733794A Process for forming a semiconductor device with ESD protection 失效
标题翻译：用于形成具有ESD保护的半导体器件的工艺
公开(公告)号：US5733794A
公开(公告)日：1998-03-31
申请号：US384177
申请日：1995-02-06
申请人： Percy Veryon Gilbert , Paul G. Y. Tsui , Shih-Wei Sun , Stephen G. Jamison
发明人： Percy Veryon Gilbert , Paul G. Y. Tsui , Shih-Wei Sun , Stephen G. Jamison
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/06 , H01L27/088 , H01L21/265
CPC分类号： H01L27/0266
摘要： A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the source and drain regions adjacent thereto. In one embodiment, the ESD protection transistor is a thick field oxide (TFO) transistor. In some cases, the halo regions may be provided with an ion implant step without the use of an extra mask. The halo regions permit the ESD protection transistor to have its breakdown voltage adjusted so that it turns on before the device it is protecting is affected by an ESD event. The use of halo regions avoids the increase in device area and adverse effects to the AC performance of the circuit being protected that are disadvantages of prior approaches.
摘要翻译：设计了具有静电放电（ESD）保护晶体管的半导体器件，其中ESD保护晶体管具有与其相邻的源极和漏极区域具有相反导电类型的晕圈。在一个实施例中，ESD保护晶体管是厚场氧化物（TFO）晶体管。在一些情况下，可以在不使用额外掩模的情况下为晕区提供离子注入步骤。光晕区域允许ESD保护晶体管调整其击穿电压，使其在保护器件受ESD事件影响之前导通。晕圈的使用避免了设备面积的增加和对被保护电路的AC性能的不利影响，这是现有方法的缺点。

5. 发明授权

US08446176B1 Reconfigurable engineering change order base cell 有权
标题翻译：可重构工程变更订单基本单元格
公开(公告)号：US08446176B1
公开(公告)日：2013-05-21
申请号：US13326556
申请日：2011-12-15
申请人： Jianan Yang , Darrin L. Hutchinson , Stephen G. Jamison
发明人： Jianan Yang , Darrin L. Hutchinson , Stephen G. Jamison
IPC分类号： H01L25/00 , H01L27/088 , H03K19/20 , H03K19/094
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/092
摘要： An integrated circuit ECO base cell module is formed with PMOS and NMOS gate electrode structures and power supply lines that are electrically separated from one another up to the second metal (M2) layer in a fixed circuit structure that may be reconfigured with one or more conductor elements formed above the M2 layer to form a predetermined circuit function.
摘要翻译：集成电路ECO基电池模块形成有PMOS和NMOS栅极电极结构和电源线，其以固定电路结构彼此电分离直到第二金属（M2）层，其可以用一个或多个导体形成在M2层上方的元件以形成预定的电路功能。

6. 发明申请

US20130049807A1 INTEGRATED CIRCUIT HAVING CRITICAL PATH VOLTAGE SCALING AND METHOD THEREFOR 有权
标题翻译：具有关键路径电压调节的集成电路及其方法
公开(公告)号：US20130049807A1
公开(公告)日：2013-02-28
申请号：US13220302
申请日：2011-08-29
申请人： JIANAN YANG , Stephen G. Jamison , David L. Medlock , Gary Waugh
发明人： JIANAN YANG , Stephen G. Jamison , David L. Medlock , Gary Waugh
IPC分类号： H03K19/0175 , G06F17/50
CPC分类号： H03K3/356156
摘要： An integrated circuit comprises logic circuitry having a plurality of signal paths. A signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths. The signal path includes a plurality of components. The plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths.
摘要翻译：集成电路包括具有多个信号路径的逻辑电路。多个信号路径的信号路径具有大于多个信号路径中的任何其它信号路径的传播延迟的传播延迟。信号路径包括多个组件。多个组件被提供有比多个信号路径中的任何其它信号路径更高的电源电压。

7. 发明申请

US20100026343A1 CLOCKED SINGLE POWER SUPPLY LEVEL SHIFTER 有权
标题翻译：时钟单电源电平变换器
公开(公告)号：US20100026343A1
公开(公告)日：2010-02-04
申请号：US12183739
申请日：2008-07-31
申请人： Jianan Yang , Wang K. Chen , Stephen G. Jamison
发明人： Jianan Yang , Wang K. Chen , Stephen G. Jamison
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/01855
摘要： First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply domain by a clocked level shifter that couples the first circuitry to the second circuitry and buffers the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage. The clocked level shifter is clocked by a signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period. The first and second nodes are precharged to establish a known state in the clocked level shifter.
摘要翻译：第一电路由第一电源域供电并提供参考第一电源域的数据信号。第二电路由与第一电源域不同的第二电源域供电。数据信号通过时钟电平移位器参考第二电源域，其将第一电路耦合到第二电路，并且仅通过使用单个电源电压将数据信号从第一电源域缓冲到第二电源域。时钟电平移位器由用于对时钟电平移位器的第一节点和第二节点进行预充电的信号计时，直到数据信号在至少一个建立时间段内有效为止。第一和第二节点被预充电以在时钟电平移位器中建立已知状态。

8. 发明授权

US07777522B2 Clocked single power supply level shifter 有权
标题翻译：时钟单电源电平转换器
公开(公告)号：US07777522B2
公开(公告)日：2010-08-17
申请号：US12183739
申请日：2008-07-31
申请人： Jianan Yang , Wang K. Chen , Stephen G. Jamison
发明人： Jianan Yang , Wang K. Chen , Stephen G. Jamison
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/01855
摘要： First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply domain by a clocked level shifter that couples the first circuitry to the second circuitry and buffers the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage. The clocked level shifter is clocked by a signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period. The first and second nodes are precharged to establish a known state in the clocked level shifter.
摘要翻译：第一电路由第一电源域供电并提供参考第一电源域的数据信号。第二电路由与第一电源域不同的第二电源域供电。数据信号通过时钟电平移位器参考第二电源域，其将第一电路耦合到第二电路，并且仅通过使用单个电源电压将数据信号从第一电源域缓冲到第二电源域。时钟电平移位器由用于对时钟电平移位器的第一节点和第二节点进行预充电的信号计时，直到数据信号在至少一个建立时间段内有效为止。第一和第二节点被预充电以在时钟电平移位器中建立已知状态。

9. 发明申请

US20090302885A1 TWO TRANSISTOR TIE CIRCUIT WITH BODY BIASING 审中-公开
标题翻译：具有身体偏转的两个晶体管电路
公开(公告)号：US20090302885A1
公开(公告)日：2009-12-10
申请号：US12134273
申请日：2008-06-06
申请人： JIANAN YANG , Wang K. Chen , Stephen G. Jamison , Arthur R. Piejko , Jun Tang
发明人： JIANAN YANG , Wang K. Chen , Stephen G. Jamison , Arthur R. Piejko , Jun Tang
IPC分类号： H03K19/003 , G05F1/00
CPC分类号： H03K19/003 , H03K2217/0018
摘要： A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node.
摘要翻译：提供了一种用于车身偏置的电路。电路包括：（1）具有第一电流端子的p型晶体管，其耦合到第一电压源，第二电流端子，控制端子和体积端子; 和（2）具有第一电流端子的n型晶体管，其耦合到不同于第一电压源的第二电压源，第二电流端子，控制端子和体积端子，其中， p型晶体管，p型晶体管的第二电流端子和n型晶体管的控制端子耦合到第一节点，其中p型晶体管的控制端子，n型晶体管的体积端子型晶体管，并且第二晶体管的第二电流端子耦合到不同于第一节点的第二节点。

10. 发明授权

US6046897A Segmented bus architecture (SBA) for electrostatic discharge (ESD) protection 失效
标题翻译：用于静电放电（ESD）保护的分段总线架构（SBA）
公开(公告)号：US6046897A
公开(公告)日：2000-04-04
申请号：US939284
申请日：1997-09-29
申请人： Jeremy C. Smith , Stephen G. Jamison
发明人： Jeremy C. Smith , Stephen G. Jamison
IPC分类号： H01L27/02 , H02H3/22
CPC分类号： H01L27/0251 , H01L27/0255 , H01L27/0266
摘要： A segmented bus architecture (800) removes certain ESD circuitry from each I/O pad cell (806, 812) and places it in a power pad cell (808, 814) or in some other unused area of the integrated circuit which incorporates the SBA. The removed ESD circuit is shared by several adjacent I/O pad cells via a segmented ESD bus. As a result, each individual I/O pad cell may be reduced in size.
摘要翻译：分段总线架构（800）从每个I / O焊盘单元（806,812）去除某些ESD电路，并将其放置在集成电路中的功率垫单元（808,814）或其他未使用的区域中。去除的ESD电路由几个相邻的I / O焊盘单元通过分段的ESD总线共享。结果，可以减小每个单独的I / O焊盘单元的尺寸。

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