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1. 发明授权

US6165846A Method of eliminating gate leakage in nitrogen annealed oxides 有权
标题翻译：消除氮退火氧化物中的栅极泄漏的方法
公开(公告)号：US6165846A
公开(公告)日：2000-12-26
申请号：US260913
申请日：1999-03-02
申请人： Timothy K. Carns , John A. Smythe, III , John A. Ransom , Bernice L. Kickel , John E. Berg
发明人： Timothy K. Carns , John A. Smythe, III , John A. Ransom , Bernice L. Kickel , John E. Berg
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/28202 , H01L27/105 , H01L27/11526 , H01L27/11546 , H01L29/518
摘要： The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. A method of realizing the improved tunnel oxide Q.sub.BD using higher post-oxidation time and temperature annealing while at the same time not degrading the quality of subsequent gate oxides is shown. The use of sacrificial oxidation and strip just prior to the transistor gate oxidation is described. This process removes the additional nitride which exists at the field edges, leading to the oxide thinning. As a result, improved tunnel oxide integrity can be achieved without degradation of high and low voltage transistors.
摘要翻译：用于EEPROM和FLASH技术的薄隧道氧化物的改进使用氮中的后氧化退火在随后的氧化膜中引起缺陷。这些表现为鸟喙处的氧化物变薄，导致高漏电。随着后氧化退火的时间和温度增加，隧道氧化物性能的提高，缺陷数量迅速增加。示出了使用更高的后氧化时间和温度退火实现改进的隧道氧化物QBD的方法，同时不降低随后的栅极氧化物的质量。描述了在晶体管栅极氧化之前使用牺牲氧化和条带。该工艺除去存在于场边缘的附加氮化物，导致氧化物变薄。结果，可以在不降低高压和低压晶体管的情况下实现改进的隧道氧化物完整性。

2. 发明授权

US07807528B1 ESD protection transistor 有权
标题翻译： ESD保护晶体管
公开(公告)号：US07807528B1
公开(公告)日：2010-10-05
申请号：US12383534
申请日：2009-03-24
申请人： John A. Ransom , Brett D. Lowe , Michael J. Westphal
发明人： John A. Ransom , Brett D. Lowe , Michael J. Westphal
IPC分类号： H01L21/8234
CPC分类号： H01L29/0847 , H01L23/60 , H01L27/0266 , H01L29/1087 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
摘要翻译：静电放电（ESD）晶体管结构包括从50微米宽的栅电极小于0.4微米的自对准外伸支架。外部支架在集成电路的普通逻辑晶体管上制造，而不会严重影响晶体管的性能。外伸支架用作植入物阻挡结构，以在悬臂附近的轻掺杂区域的两侧形成第一和第二漏区。自对准外伸支架及其下方的轻掺杂区域用于将ESD事件的远离通道区域的雪崩击穿位置移动。当较少的“热载体”电子在栅极氧化物中积聚时，耐久性得到延长。至少100毫安的电流可以流入漏极，然后通过ESD晶体管结构超过30秒的时间，而不会导致ESD晶体管结构的灾难性故障。

3. 发明授权

US07927944B1 ESD protection transistor 有权
公开(公告)号：US07927944B1
公开(公告)日：2011-04-19
申请号：US12807669
申请日：2010-09-10
申请人： John A. Ransom , Brett D. Lowe , Michael J. Westphal
发明人： John A. Ransom , Brett D. Lowe , Michael J. Westphal
IPC分类号： H01L21/8234
CPC分类号： H01L29/0847 , H01L23/60 , H01L27/0266 , H01L29/1087 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

4. 发明授权

US07884489B1 Press-fit integrated circuit package involving compressed spring contact beams 有权
标题翻译：压入式集成电路封装，包括压缩弹簧接触梁
公开(公告)号：US07884489B1
公开(公告)日：2011-02-08
申请号：US12657094
申请日：2010-01-12
申请人： Thomas Stortini , John A. Ransom
发明人： Thomas Stortini , John A. Ransom
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40 , H01L23/495 , H01L23/485 , H01L23/498
CPC分类号： H01L23/49506 , H01L23/13 , H01L23/49541 , H01L23/49811 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/72 , H01L24/90 , H01L2224/0401 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73251 , H01L2224/81901 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/72
摘要： An insulative substrate includes a plurality of flexible retaining clips and a plurality of alignment and retaining pins. A metal leadframe includes a plurality of leads. Each lead terminates in a spring contact beam portion. The leadframe is attached to the substrate (for example, by fitting a hole in each lead over a corresponding alignment and retaining pin and then thermally deforming the pin to hold the lead in place). An integrated circuit is press-fit down through the retaining clips such that pads on the face side of the integrated circuit contact and compress the spring contact beams of the leads. After the press-fit step, the retaining clips hold the integrated circuit in place. The resulting assembly is encapsulated. In a cutting and bending step, the leads are singulated and formed to have a desired shape. The resulting low-cost package involves no wire-bonding and no flip-chip bond bump forming steps.
摘要翻译：绝缘衬底包括多个柔性保持夹和多个对准和保持销。金属引线框架包括多个引线。每个引线终止于弹簧接触梁部分。引线框架连接到基板上（例如，通过在相应的对准和固定销中的每个引线中安装一个孔，然后使引脚热变形以将引线保持在适当位置）。集成电路通过固定夹压配合使得集成电路的正面侧的焊盘接触并压缩引线的弹簧接触梁。在压配合步骤之后，固定夹将集成电路固定到位。所得组件被封装。在切割和弯曲步骤中，引线被切割并形成为具有期望的形状。所得到的低成本封装不涉及引线接合和没有倒装芯片接合凸块形成步骤。

5. 发明授权

US08093121B1 ESD protection transistor 有权
标题翻译： ESD保护晶体管
公开(公告)号：US08093121B1
公开(公告)日：2012-01-10
申请号：US13248520
申请日：2011-09-29
申请人： John A. Ransom , Brett D. Lowe , Michael J. Westphal
发明人： John A. Ransom , Brett D. Lowe , Michael J. Westphal
IPC分类号： H01L21/8238
CPC分类号： H01L29/0847 , H01L23/60 , H01L27/0266 , H01L29/1087 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
摘要翻译：静电放电（ESD）晶体管结构包括从50微米宽的栅电极小于0.4微米的自对准外伸支架。外部支架在集成电路的普通逻辑晶体管上制造，而不会严重影响晶体管的性能。外伸支架用作植入物阻挡结构，以在悬臂附近的轻掺杂区域的两侧形成第一和第二漏区。自对准外伸支架及其下方的轻掺杂区域用于将ESD事件的远离通道区域的雪崩击穿位置移动。当较少的“热载体”电子在栅极氧化物中积聚时，耐久性得到延长。至少100毫安的电流可以流入漏极，然后通过ESD晶体管结构超过30秒的时间，而不会导致ESD晶体管结构的灾难性故障。

6. 发明授权

US08062941B1 ESD protection transistor 有权
标题翻译： ESD保护晶体管
公开(公告)号：US08062941B1
公开(公告)日：2011-11-22
申请号：US13065940
申请日：2011-04-02
申请人： John A. Ransom , Brett D. Lowe , Michael J. Westphal
发明人： John A. Ransom , Brett D. Lowe , Michael J. Westphal
IPC分类号： H01L21/8238
CPC分类号： H01L29/0847 , H01L23/60 , H01L27/0266 , H01L29/1087 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
摘要翻译：静电放电（ESD）晶体管结构包括从50微米宽的栅电极小于0.4微米的自对准外伸支架。外部支架在集成电路的普通逻辑晶体管上制造，而不会严重影响晶体管的性能。外伸支架用作植入物阻挡结构，以在悬臂附近的轻掺杂区域的两侧形成第一和第二漏区。自对准外伸支架及其下方的轻掺杂区域用于将ESD事件的远离通道区域的雪崩击穿位置移动。当较少的“热载体”电子在栅极氧化物中积聚时，耐久性得到延长。至少100毫安的电流可以流入漏极，然后通过ESD晶体管结构超过30秒的时间，而不会导致ESD晶体管结构的灾难性故障。

7. 发明授权

US07683494B1 Press-fit integrated circuit package involving compressed spring contact beams 有权
标题翻译：压入式集成电路封装，包括压缩弹簧接触梁
公开(公告)号：US07683494B1
公开(公告)日：2010-03-23
申请号：US12214479
申请日：2008-06-18
申请人： Thomas Stortini , John A. Ransom
发明人： Thomas Stortini , John A. Ransom
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40 , H01L23/495 , H01L23/485 , H01L23/498
CPC分类号： H01L23/49506 , H01L23/13 , H01L23/49541 , H01L23/49811 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/72 , H01L24/90 , H01L2224/0401 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73251 , H01L2224/81901 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/72
摘要： An insulative substrate includes a plurality of flexible retaining clips and a plurality of alignment and retaining pins. A metal leadframe includes a plurality of leads. Each lead terminates in a spring contact beam portion. The leadframe is attached to the substrate (for example, by fitting a hole in each lead over a corresponding alignment and retaining pin and then thermally deforming the pin to hold the lead in place). An integrated circuit is press-fit down through the retaining clips such that pads on the face side of the integrated circuit contact and compress the spring contact beams of the leads. After the press-fit step, the retaining clips hold the integrated circuit in place. The resulting assembly is encapsulated. In a cutting and bending step, the leads are singulated and formed to have a desired shape. The resulting low-cost package involves no wire-bonding and no flip-chip bond bump forming steps.
摘要翻译：绝缘衬底包括多个柔性保持夹和多个对准和保持销。金属引线框架包括多个引线。每个引线终止于弹簧接触梁部分。引线框架连接到基板上（例如，通过在相应的对准和固定销中的每个引线中安装一个孔，然后使引脚热变形以将引线保持在适当位置）。集成电路通过固定夹压配合使得集成电路的正面侧的焊盘接触并压缩引线的弹簧接触梁。在压配合步骤之后，固定夹将集成电路固定到位。所得组件被封装。在切割和弯曲步骤中，引线被切割并形成为具有期望的形状。所得到的低成本封装不涉及引线接合和没有倒装芯片接合凸块形成步骤。

8. 发明授权

US07508038B1 ESD protection transistor 有权
标题翻译： ESD保护晶体管
公开(公告)号：US07508038B1
公开(公告)日：2009-03-24
申请号：US11118680
申请日：2005-04-29
申请人： John A. Ransom , Brett D. Lowe , Michael J. Westphal
发明人： John A. Ransom , Brett D. Lowe , Michael J. Westphal
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L23/60 , H01L27/0266 , H01L29/1087 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
摘要翻译：静电放电（ESD）晶体管结构包括从50微米宽的栅电极小于0.4微米的自对准外伸支架。外部支架在集成电路的普通逻辑晶体管上制造，而不会严重影响晶体管的性能。外伸支架用作植入物阻挡结构，以在悬臂附近的轻掺杂区域的两侧形成第一和第二漏区。自对准外伸支架及其下方的轻掺杂区域用于将ESD事件的远离通道区域的雪崩击穿位置移动。当较少的“热载体”电子在栅极氧化物中积聚时，耐久性得到延长。至少100毫安的电流可以流入漏极，然后通过ESD晶体管结构超过30秒的时间，而不会导致ESD晶体管结构的灾难性故障。

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