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    • 9. 发明授权
    • Method and apparatus for built-in self-repair of memory storage arrays
    • 用于存储器阵列内置自修复的方法和装置
    • US06259637B1
    • 2001-07-10
    • US09728285
    • 2000-12-01
    • Timothy J. WoodRaghuram S. TupuriGerald D. Zuraski, Jr.
    • Timothy J. WoodRaghuram S. TupuriGerald D. Zuraski, Jr.
    • G11C700
    • G11C29/4401G11C29/44
    • An integrated circuit device includes a memory array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns. First and second redundant rows of memory cells and a first redundant column of memory cells are provided. A test circuit is coupled to the memory array and is adapted to test a plurality of memory cells coupled to each of the plurality of rows. A control circuit is coupled to the test circuit and is adapted to receive test results from the test circuit, the control circuit being adapted to respond to a detection of a defective memory cell to determine an assignment of at least one of the first and second redundant rows and first redundant column. A first register is coupled to the control circuit and adapted to receive an assignment of the first redundant row in response to a determination by the control circuit, a second register is coupled to the control circuit and adapted to receive an assignment of the first redundant column in response to a determination by the control circuit, and a third register is coupled to the control circuit and adapted to receive an assignment of the second redundant row in response to a determination by the control circuit.
    • 集成电路装置包括具有以多行和多列布置的多个存储单元的存储器阵列。 提供存储单元的第一和第二冗余行和存储器单元的第一冗余列。 测试电路耦合到存储器阵列,并且适于测试耦合到多个行中的每一行的多个存储器单元。 控制电路耦合到测试电路并且适于从测试电路接收测试结果,所述控制电路适于响应于有缺陷的存储器单元的检测,以确定第一和第二冗余中的至少一个的分配 行和第一冗余列。 第一寄存器耦合到控制电路并且适于响应于控制电路的确定而接收第一冗余行的分配,第二寄存器耦合到控制电路并且适于接收第一冗余列的分配 响应于控制电路的确定,并且第三寄存器耦合到控制电路,并且适于响应于控制电路的确定而接收第二冗余行的分配。