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1. 发明授权

US06387754B2 Method of forming an on-chip decoupling capacitor with bottom hardmask 失效
标题翻译：用底部硬掩模形成片上去耦电容器的方法
公开(公告)号：US06387754B2
公开(公告)日：2002-05-14
申请号：US09887381
申请日：2001-06-22
申请人： Timothy J. Dalton , Andrew P. Cowley , Peter A. Emmi , Erdem Kaltalioglu , Vincent J. McGahay
发明人： Timothy J. Dalton , Andrew P. Cowley , Peter A. Emmi , Erdem Kaltalioglu , Vincent J. McGahay
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/32136 , H01L21/32139
摘要： An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.
摘要翻译：片上垂直堆叠的去耦电容器包括形成在电容器电介质和下电极之间的硬掩模膜。用于形成电容器的制造工艺利用了硬掩膜，并且使电容器能够在低k电介质材料上形成。由于硬掩模的存在，在用于形成电容器的蚀刻和剥离工艺期间，底层的低k介电材料的攻击被抑制。低k电介质膜提供了在低k电介质材料中形成的相邻导线之间降低的寄生电容，因此提供了更高的集成度。

2. 发明授权

US06278147B1 On-chip decoupling capacitor with bottom hardmask 失效
标题翻译：带底部硬掩模的片上去耦电容
公开(公告)号：US06278147B1
公开(公告)日：2001-08-21
申请号：US09484359
申请日：2000-01-18
申请人： Timothy J. Dalton , Andrew P. Cowley , Peter A. Emmi , Erdem Kaltalioglu , Vincent J. McGahay
发明人： Timothy J. Dalton , Andrew P. Cowley , Peter A. Emmi , Erdem Kaltalioglu , Vincent J. McGahay
IPC分类号： H01L2976
CPC分类号： H01L28/75 , H01L21/32136 , H01L21/32139
摘要： An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.
摘要翻译：片上垂直堆叠的去耦电容器包括形成在电容器电介质和下电极之间的硬掩模膜。用于形成电容器的制造工艺利用了硬掩膜，并且使电容器能够在低k电介质材料上形成。由于硬掩模的存在，在用于形成电容器的蚀刻和剥离工艺期间，抑制底层低k电介质材料的攻击。低k电介质膜提供了在低k电介质材料中形成的相邻导线之间降低的寄生电容，因此提供了更高的集成度。

3. 发明授权

US06268621B1 Vertical channel field effect transistor 失效
标题翻译：垂直沟道场效应晶体管
公开(公告)号：US06268621B1
公开(公告)日：2001-07-31
申请号：US09366147
申请日：1999-08-03
申请人： Peter A. Emmi , Byeongju Park
发明人： Peter A. Emmi , Byeongju Park
IPC分类号： H01L27108
CPC分类号： H01L29/66666 , H01L21/84 , H01L27/1203 , H01L29/7827 , H01L29/78642
摘要： A vertical channel field effect transistor and a process of manufacturing the same. The vertical channel field effect transistor is disposed on a surface of a substrate and comprises an epitaxial silicon stack having a bottom terminal comprising heavily doped silicon, a channel comprising lightly doped silicon of opposite doping type from the bottom terminal, and a top terminal comprising heavily doped silicon of the same doping type as the bottom terminal. The vertical channel field effect transistor also comprises a gate dielectric layer covering at least a portion of the bottom terminal, the channel, and the top terminal, and a gate in contact with the gate dielectric layer. The gate is positioned adjacent the channel and adjacent at least a portion of the bottom terminal and top terminal. The channel has a thickness between the bottom terminal and the top terminal from about 50 angstroms to about 800 angstroms.
摘要翻译：一种垂直沟道场效应晶体管及其制造方法。垂直沟道场效应晶体管设置在衬底的表面上，并且包括具有包括重掺杂硅的底部端子的外延硅堆叠，包括与底部端子相反掺杂型的轻掺杂硅的沟道，以及包括大量掺杂的顶端与底端相同的掺杂类型的掺杂硅。垂直沟道场效应晶体管还包括覆盖底部端子，沟道和顶部端子的至少一部分的栅极介电层和与栅极介电层接触的栅极。栅极定位在通道附近并且邻近底部端子和顶部端子的至少一部分。该通道在底部端子和顶部端子之间具有约50埃至约800埃的厚度。

4. 发明授权

US06488778B1 Apparatus and method for controlling wafer environment between thermal clean and thermal processing 有权
标题翻译：用于控制热清洁和热处理之间的晶片环境的装置和方法
公开(公告)号：US06488778B1
公开(公告)日：2002-12-03
申请号：US09527698
申请日：2000-03-16
申请人： Arne W. Ballantine , Peter A. Emmi , Walter J. Frey , Michael J. Gambero , Neena Garg , Byeongju Park , Donald L. Wilson
发明人： Arne W. Ballantine , Peter A. Emmi , Walter J. Frey , Michael J. Gambero , Neena Garg , Byeongju Park , Donald L. Wilson
IPC分类号： C23C1600
CPC分类号： H01L21/67115 , C23C16/54 , H01L21/67109 , Y10S414/135 , Y10S414/137 , Y10S414/139
摘要： An apparatus and method for controlling wafer temperature and environment is provided. The apparatus includes a batch processing fixture for batch processing wafers at a first elevated temperature. The batch of wafers is not substantially ramped in temperature within the batch processing fixture. The apparatus also includes a single wafer processing apparatus for rapidly ramping temperature of a wafer of the batch from the first elevated temperature wherein a uniform temperature across the wafer is maintained during the ramping. Another embodiment of the apparatus (10) includes an RTP chamber (20) having an inert or reducing environment and that includes a pedestal (24) for holding a single wafer (16) and a heater unit (22) arranged so as to uniformly and rapidly heat the single wafer. The apparatus also includes a cooling chamber (30) having an inert or reducing environment and located adjacent the RTP chamber and selectively open thereto, and includes a pedestal (34) for holding the single wafer, a first loading chamber (40) having an inert or reducing environment and located adjacent the cooling chamber and selectively opened thereto, and having a cassette (44) for holding one or more wafers. The apparatus also includes a thermal processing chamber (50), such as an LPCVD furnace, located adjacent the loading chamber and arranged to receive the cassette so as to perform a thermal process of the wafers in the cassette.
摘要翻译：提供了一种用于控制晶片温度和环境的设备和方法。该设备包括用于在第一高温下批处理晶片的批处理夹具。该批晶片在批处理固定装置内的温度基本上不斜坡。该装置还包括一个单晶片处理装置，用于从第一升高温度快速地升高批料晶片的温度，其中在斜坡期间保持跨晶片的均匀温度。装置（10）的另一实施例包括具有惰性或还原环境的RTP室（20），其包括用于保持单个晶片（16）的基座（24）和加热器单元（22）快速加热单晶片。该装置还包括具有惰性或还原环境并且位于RTP室附近并选择性地向其开放的冷却室（30），并且包括用于保持单个晶片的基座（34），具有惰性的第一装载室（40）或减少环境并且位于冷却室附近并选择性地向其敞开，并且具有用于保持一个或多个晶片的盒（44）。该设备还包括位于加载室附近并布置成接收盒以便对盒中的晶片进行热处理的热处理室（诸如LPCVD炉）。

5. 发明授权

US06178660B2 Pass-through semiconductor wafer processing tool and process for gas treating a moving semiconductor wafer 失效
标题翻译：直通半导体晶片处理工具和用于气体处理移动半导体晶片的工艺
公开(公告)号：US06178660B2
公开(公告)日：2001-01-30
申请号：US09366146
申请日：1999-08-03
申请人： Peter A. Emmi , Byeongju Park
发明人： Peter A. Emmi , Byeongju Park
IPC分类号： F26B504
CPC分类号： H01L21/67017 , H01L21/67069
摘要： A pass-through, wafer-processing tool for treating a moving semiconductor wafer with a process gas. The tool comprises an open-ended, non-isolated processing module having a wafer path through the module, vacuum manifolds mounted adjacent the wafer entry to and wafer exit from the module, and a gas manifold between the vacuum manifolds adapted to direct process gas onto the moving wafer. The gas manifold may deliver plasma ions generated by a remote plasma unit outside the module. Instead, a plasma may be generated inside the pass-through, wafer processing tool and, if so, the tool further comprises a top electrode mounted above the wafer passage. A wafer handler, which may be a robotic handler, carries the wafer through the wafer passage and serves as a bottom electrode. The gas manifold delivers reactive gas between the moving wafer and the top electrode while an RF source connected to the top electrode delivers sufficient RF energy to generate a plasma from the reactive gas between the top electrode and the wafer. One or more pass-through, wafer-processing tools may be part of an integrated system of semiconductor wafer processing tools. Processes for treating semiconductor wafers with process gas using the above apparatus are also disclosed.
摘要翻译：一种用工艺气体处理移动的半导体晶片的直通晶片处理工具。该工具包括具有穿过模块的晶片通道的开放式非隔离处理模块，邻近晶片入口安装的真空歧管和晶片从模块出口，以及适于将工艺气体引导到真空歧管之间的气体歧管移动晶片。气体歧管可以传递由模块外部的远程等离子体单元产生的等离子体离子。相反，可以在直通，晶片加工工具内部产生等离子体，如果是，则该工具还包括安装在晶片通道上方的顶部电极。可以是机器人处理器的晶片处理器将晶片通过晶片通道并用作底部电极。气体歧管在移动的晶片和顶部电极之间输送反应性气体，而连接到顶部电极的RF源提供足够的RF能量以从顶部电极和晶片之间的反应性气体产生等离子体。一个或多个直通晶片处理工具可以是半导体晶片处理工具的集成系统的一部分。还公开了使用上述装置用工艺气体处理半导体晶片的工艺。

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