专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100058026A1 LOADING ENTRIES INTO A TLB IN HARDWARE VIA INDIRECT TLB ENTRIES 有权
标题翻译：通过间接TLB入口将其装入硬件中的TLB
公开(公告)号：US20100058026A1
公开(公告)日：2010-03-04
申请号：US12548213
申请日：2009-08-26
申请人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
发明人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
IPC分类号： G06F12/06
CPC分类号： G06F12/1027 , G06F12/1009
摘要： An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.
摘要翻译：一种用于通过间接TLB条目在硬件中将条目加载到翻译后备缓冲器（TLB）中的增强机制。在一个实施例中，如果在TLB中没有找到与给定虚拟地址相关联的直接TLB条目，则检查TLB与给定虚拟地址相关联的间接TLB条目。每个间接TLB条目提供与指定范围的虚拟地址相关联的页表的真实地址，并且包括页表条目数组。如果在TLB中找到与给定虚拟地址相关联的间接TLB条目，则通过组合来自间接TLB条目的实际地址字段和来自给定虚拟地址的比特来产生计算的地址，获得页表条目（PTE）通过从所计算的地址的存储器读取一个字，并且将PTE作为直接TLB条目加载到TLB中。

2. 发明授权

US08296547B2 Loading entries into a TLB in hardware via indirect TLB entries 有权
标题翻译：通过间接TLB条目将条目加载到硬件中的TLB中
公开(公告)号：US08296547B2
公开(公告)日：2012-10-23
申请号：US12548213
申请日：2009-08-26
申请人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
发明人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/1009
摘要： An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.
摘要翻译：一种用于通过间接TLB条目在硬件中将条目加载到翻译后备缓冲器（TLB）中的增强机制。在一个实施例中，如果在TLB中没有找到与给定虚拟地址相关联的直接TLB条目，则检查TLB与给定虚拟地址相关联的间接TLB条目。每个间接TLB条目提供与指定范围的虚拟地址相关联的页表的真实地址，并且包括页表条目数组。如果在TLB中找到与给定虚拟地址相关联的间接TLB条目，则通过组合来自间接TLB条目的实际地址字段和来自给定虚拟地址的比特来产生计算的地址，获得页表条目（PTE）通过从所计算的地址的存储器读取一个字，并且将PTE作为直接TLB条目加载到TLB中。

3. 发明申请

US20060208928A1 Encoding scheme to resist code injection attacks 审中-公开
标题翻译：编码方案，以抵御代码注入攻击
公开(公告)号：US20060208928A1
公开(公告)日：2006-09-21
申请号：US11011992
申请日：2004-12-14
申请人： Paul Mackerras , Paul Russell
发明人： Paul Mackerras , Paul Russell
IPC分类号： H03M7/00
CPC分类号： G06F9/3017 , G06F21/71 , G06F21/72
摘要： A method and system are provided for encoding program instructions, and for decoding the encoded program instructions prior to execution. An encoded set of program instructions is provided by combining a single page of decode instructions with a set of unencoded program instructions. The page of decode instructions is set at an address which may be located by means of a hardware register. Prior to execution of the encoded set of program instructions, the location of the decode page is ascertained by consulting the assigned hardware register. The decode page is combined with the encoded program instructions to produce a stream of executable program instructions.
摘要翻译：提供了一种方法和系统，用于对程序指令进行编码，并在执行之前对编码的程序指令进行解码。通过将单页解码指令与一组未编码的程序指令组合来提供编码的程序指令集。解码指令的页面被设置在可以通过硬件寄存器定位的地址。在执行编码的程序指令集之前，通过咨询分配的硬件寄存器来确定解码页的位置。解码页面与编码的程序指令组合以产生可执行程序指令流。

4. 发明授权

US07219210B2 Memory allocation to multiple computing units 有权
标题翻译：内存分配到多个计算单元
公开(公告)号：US07219210B2
公开(公告)日：2007-05-15
申请号：US10812773
申请日：2004-03-30
申请人： Paul F. Russell , Paul Mackerras
发明人： Paul F. Russell , Paul Mackerras
IPC分类号： G06F12/10
CPC分类号： G06F12/0284
摘要： Memory allocation to multiple computing units is disclosed. A static offset for each computing unit is determined, and a portion of memory is allocated for each computing unit, and remapped into a contiguous logical region that is addressable by a pointer plus the static offset. The portion of the memory is dynamically passed out to each computing unit as the computing units need memory. Upon the initial contiguous memory being completely passed out to the computing units, a number of physically non-contiguous sections of memory are mapped into another logically contiguous section of memory. A portion of this logically contiguous section of memory is allocated for each computing unit, and is addressable by a pointer plus the static offset that was previously determined. The portion of the logically contiguous section of memory can be dynamically passed out to each computing unit as the computing units need memory.
摘要翻译：公开了对多个计算单元的内存分配。确定每个计算单元的静态偏移量，并且为每个计算单元分配一部分存储器，并将其重新映射到可由指针加上静态偏移量的可连续逻辑区域。当计算单元需要存储器时，存储器的一部分被动态地传送到每个计算单元。在初始连续存储器被完全传递到计算单元时，存储器的物理上非连续部分的数量被映射到另一逻辑上连续的存储器部分。该逻辑连续部分的存储器的一部分被分配给每个计算单元，并且可由指针加上先前确定的静态偏移量来寻址。当计算单元需要存储器时，存储器的逻辑连续部分的部分可以被动态地传递到每个计算单元。

5. 发明申请

US20050223184A1 Memory allocation to multiple computing units 有权
标题翻译：内存分配到多个计算单元
公开(公告)号：US20050223184A1
公开(公告)日：2005-10-06
申请号：US10812773
申请日：2004-03-30
申请人： Paul Russell , Paul Mackerras
发明人： Paul Russell , Paul Mackerras
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0284
摘要： Memory allocation to multiple computing units is disclosed. A static offset for each computing unit is determined, and a portion of memory is allocated for each computing unit, and remapped into a contiguous logical region that is addressable by a pointer plus the static offset. The portion of the memory is dynamically passed out to each computing unit as the computing units need memory. Upon the initial contiguous memory being completely passed out to the computing units, a number of physically non-contiguous sections of memory are mapped into another logically contiguous section of memory. A portion of this logically contiguous section of memory is allocated for each computing unit, and is addressable by a pointer plus the static offset that was previously determined. The portion of the logically contiguous section of memory can be dynamically passed out to each computing unit as the computing units need memory.
摘要翻译：公开了对多个计算单元的内存分配。确定每个计算单元的静态偏移量，并且为每个计算单元分配一部分存储器，并将其重新映射到可由指针加上静态偏移量的可连续逻辑区域。当计算单元需要存储器时，存储器的一部分被动态地传送到每个计算单元。在初始连续存储器被完全传递到计算单元时，存储器的物理上非连续部分的数量被映射到另一逻辑上连续的存储器部分。该逻辑连续部分的存储器的一部分被分配给每个计算单元，并且可由指针加上先前确定的静态偏移量来寻址。当计算单元需要存储器时，存储器的逻辑连续部分的部分可以被动态地传递到每个计算单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式