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1. 发明申请

US20100058026A1 LOADING ENTRIES INTO A TLB IN HARDWARE VIA INDIRECT TLB ENTRIES 有权
标题翻译：通过间接TLB入口将其装入硬件中的TLB
公开(公告)号：US20100058026A1
公开(公告)日：2010-03-04
申请号：US12548213
申请日：2009-08-26
申请人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
发明人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
IPC分类号： G06F12/06
CPC分类号： G06F12/1027 , G06F12/1009
摘要： An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.
摘要翻译：一种用于通过间接TLB条目在硬件中将条目加载到翻译后备缓冲器（TLB）中的增强机制。在一个实施例中，如果在TLB中没有找到与给定虚拟地址相关联的直接TLB条目，则检查TLB与给定虚拟地址相关联的间接TLB条目。每个间接TLB条目提供与指定范围的虚拟地址相关联的页表的真实地址，并且包括页表条目数组。如果在TLB中找到与给定虚拟地址相关联的间接TLB条目，则通过组合来自间接TLB条目的实际地址字段和来自给定虚拟地址的比特来产生计算的地址，获得页表条目（PTE）通过从所计算的地址的存储器读取一个字，并且将PTE作为直接TLB条目加载到TLB中。

2. 发明授权

US08296547B2 Loading entries into a TLB in hardware via indirect TLB entries 有权
标题翻译：通过间接TLB条目将条目加载到硬件中的TLB中
公开(公告)号：US08296547B2
公开(公告)日：2012-10-23
申请号：US12548213
申请日：2009-08-26
申请人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
发明人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/1009
摘要： An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.
摘要翻译：一种用于通过间接TLB条目在硬件中将条目加载到翻译后备缓冲器（TLB）中的增强机制。在一个实施例中，如果在TLB中没有找到与给定虚拟地址相关联的直接TLB条目，则检查TLB与给定虚拟地址相关联的间接TLB条目。每个间接TLB条目提供与指定范围的虚拟地址相关联的页表的真实地址，并且包括页表条目数组。如果在TLB中找到与给定虚拟地址相关联的间接TLB条目，则通过组合来自间接TLB条目的实际地址字段和来自给定虚拟地址的比特来产生计算的地址，获得页表条目（PTE）通过从所计算的地址的存储器读取一个字，并且将PTE作为直接TLB条目加载到TLB中。

3. 发明申请

US20130007408A1 METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES 失效
标题翻译：用于管理翻译实体的不同级别的虚拟机的物理存储器访问的软件控制的缓存的方法和装置
公开(公告)号：US20130007408A1
公开(公告)日：2013-01-03
申请号：US13616515
申请日：2012-09-14
申请人： Hubertus Franke , Benjamin Herrenschmidt , Jon K. Kriegel , Andrew M. Theurer , James Xenidis
发明人： Hubertus Franke , Benjamin Herrenschmidt , Jon K. Kriegel , Andrew M. Theurer , James Xenidis
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/4555 , G06F2212/651
摘要： A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
摘要翻译：公开了一种允许客户操作系统（客户操作系统）直接修改TLB中的条目而不涉及管理程序的方法和系统。客户操作系统在收到客户端TLB未命中异常时，向逻辑发出TLBWE（TLB写入条目）指令。该逻辑在管理员模式下运行TLBWE指令，而不调用管理程序。 TLB可以包含访客页表中的条目和主页页表中的条目。

4. 发明授权

US08275971B2 Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities 有权
标题翻译：用于管理在不同级别的翻译实体之间翻译虚拟机的物理存储器访问的软件控制缓存的方法和装置
公开(公告)号：US08275971B2
公开(公告)日：2012-09-25
申请号：US12199381
申请日：2008-08-27
申请人： Hubertus Franke , Benjamin Herrenschmidt , Jon K. Kriegel , Andrew M. Theurer , James Xenidis
发明人： Hubertus Franke , Benjamin Herrenschmidt , Jon K. Kriegel , Andrew M. Theurer , James Xenidis
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/4555 , G06F2212/651
摘要： A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic executes the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
摘要翻译：公开了一种允许客户操作系统（客户操作系统）直接修改TLB中的条目而不涉及管理程序的方法和系统。客户操作系统在收到客户端TLB未命中异常时，向逻辑发出TLBWE（TLB写入条目）指令。该逻辑在管理员模式下执行TLBWE指令，而不调用管理程序。 TLB可以包含访客页表中的条目和主页页表中的条目。

5. 发明授权

US08688953B2 Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities 失效
标题翻译：用于管理在不同级别的翻译实体之间翻译虚拟机的物理存储器访问的软件控制缓存的方法和装置
公开(公告)号：US08688953B2
公开(公告)日：2014-04-01
申请号：US13616515
申请日：2012-09-14
申请人： Hubertus Franke , Benjamin Herrenschmidt , Jon K. Kriegel , Andrew M. Theurer , James Xenidis
发明人： Hubertus Franke , Benjamin Herrenschmidt , Jon K. Kriegel , Andrew M. Theurer , James Xenidis
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/4555 , G06F2212/651
摘要： A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
摘要翻译：公开了一种允许客户操作系统（客户操作系统）直接修改TLB中的条目而不涉及管理程序的方法和系统。客户操作系统在收到客户端TLB未命中异常时，向逻辑发出TLBWE（TLB写入条目）指令。该逻辑在管理员模式下运行TLBWE指令，而不调用管理程序。 TLB可以包含访客页表中的条目和主页页表中的条目。

6. 发明申请

US20100058358A1 METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES 有权
标题翻译：用于管理翻译实体的不同级别的虚拟机的物理存储器访问的软件控制的缓存的方法和装置
公开(公告)号：US20100058358A1
公开(公告)日：2010-03-04
申请号：US12199381
申请日：2008-08-27
申请人： Hubertus Franke , Benjamin Herrenschmidt , Jon K. Kriegel , Andrew M. Theurer , James Xenidis
发明人： Hubertus Franke , Benjamin Herrenschmidt , Jon K. Kriegel , Andrew M. Theurer , James Xenidis
IPC分类号： G06F9/54 , G06F12/10 , G06F9/455 , G06F12/08
CPC分类号： G06F12/1027 , G06F9/4555 , G06F2212/651
摘要： A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic executes the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
摘要翻译：公开了一种允许客户操作系统（客户操作系统）直接修改TLB中的条目而不涉及管理程序的方法和系统。客户操作系统在收到客户端TLB未命中异常时，向逻辑发出TLBWE（TLB写入条目）指令。该逻辑在管理员模式下执行TLBWE指令，而不调用管理程序。 TLB可以包含访客页表中的条目和主页页表中的条目。

7. 发明授权

US07752413B2 Method and apparatus for communicating between threads 有权
标题翻译：用于在线程之间进行通信的方法和装置
公开(公告)号：US07752413B2
公开(公告)日：2010-07-06
申请号：US11567882
申请日：2006-12-07
申请人： Russell Dean Hoover , Jon K. Kriegel , Eric Oliver Mejdrich , Robert Allen Shearer
发明人： Russell Dean Hoover , Jon K. Kriegel , Eric Oliver Mejdrich , Robert Allen Shearer
IPC分类号： G06F12/00
CPC分类号： G06T15/50 , G06T15/06
摘要： A method and apparatus for communicating between threads in a processor. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.
摘要翻译：一种用于在处理器中的线程之间进行通信的方法和装置。该方法包括在收件箱的处理器中预留高速缓存的第一部分。收件箱与由处理器执行的第一个线程相关联。该方法还包括从第二线程接收分组，其中分组包括接入请求。该方法还包括使用收件箱控制电路来收件箱来处理接收到的分组并且确定是否授予包含在分组中的接入请求。

8. 发明申请

US20090307714A1 NETWORK ON CHIP WITH AN I/O ACCELERATOR 失效
标题翻译：使用I / O加速器的芯片上的网络
公开(公告)号：US20090307714A1
公开(公告)日：2009-12-10
申请号：US12135364
申请日：2008-06-09
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F9/54
CPC分类号： G06F9/546 , G06F15/7825 , H04L45/00
摘要： Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.
摘要翻译：芯片上的数据处理（“NOC”）包括IP块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应于网络; 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段在IP块上的执行线程上执行; 并且所述IP块中的至少一个包括向所述至少一个IP块执行至少一些数据通信业务的输入/输出（'I / O'）加速器。

9. 发明申请

US20090210592A1 Network On Chip With A Low Latency, High Bandwidth Application Messaging Interconnect 有权
标题翻译：网络片上低延迟，高带宽应用程序消息传递互连
公开(公告)号：US20090210592A1
公开(公告)日：2009-08-20
申请号：US12031733
申请日：2008-02-15
申请人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
发明人： Russell D. Hoover , Jon K. Kriegel , Eric O. Mejdrich
IPC分类号： G06F13/42 , G06F13/38
CPC分类号： G06F13/4027
摘要： A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), and bus interface controllers (108); each IP block adapted to the data communications bus through a memory communications controller and a bus interface controller; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between an IP block and memory; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between one of the IP blocks and other IP blocks; each IP block adapted to the data communications bus by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译：片上网络（NOC）和NOC数据处理方法，NOC包括集成处理器（IP）块，数据通信总线（110），存储器通信控制器（106）和总线接口控制器 108）; 每个IP块通过存储器通信控制器和总线接口控制器适应于数据通信总线; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和存储器之间的存储器寻址通信; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和其它IP块之一之间的存储器寻址通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应数据通信总线。

10. 发明授权

US07089341B2 Method and apparatus for supporting interrupt devices configured for a particular architecture on a different platform 失效
标题翻译：用于支持在不同平台上为特定架构配置的中断装置的方法和装置
公开(公告)号：US07089341B2
公开(公告)日：2006-08-08
申请号：US10815247
申请日：2004-03-31
申请人： Jon K. Kriegel
发明人： Jon K. Kriegel
IPC分类号： G06F13/24 , G06F3/00
CPC分类号： G06F13/24
摘要： Method and apparatus for supporting interrupt devices configured for a specific architecture (e.g., APIC-based software and hardware) on a different platform (e.g., a PowerPC platform). One embodiment provides an apparatus for passing interrupts from one or more devices configured for a specific interrupt architecture to one or more processors not designed for the specific interrupt architecture, comprising: an abstraction layer comprising a first plurality of registers conforming to the specific interrupt architecture; and an implementation dependent layer, disposed in communication between the abstraction layer and the one or more processors, comprising a second plurality of registers which correspond to the first plurality of registers, wherein the implementation dependent layer is configured to receive interrupts and forward received interrupts to the one or more processors and to read and write data to the second plurality of registers in response to interrupts processed through the one or more processor.
摘要翻译：用于支持在不同平台（例如，PowerPC平台）上为特定架构（例如，基于APIC的软件和硬件）配置的中断设备的方法和装置。一个实施例提供了一种用于将针对特定中断架构配置的一个或多个设备的中断的中断传送到不为特定中断体系结构设计的一个或多个处理器的装置，包括：抽象层，包括符合特定中断架构的第一多个寄存器; 以及设置在所述抽象层和所述一个或多个处理器之间的通信中的实现依赖层，包括对应于所述第一多个寄存器的第二多个寄存器，其中所述实现相关层被配置为接收中断并将接收的中断转发到所述一个或多个处理器并且响应于通过所述一个或多个处理器处理的中断而将数据读取和写入到所述第二多个寄存器。

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