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    • 1. 发明授权
    • Computer system and method for executing threads of execution with
reduced run-time memory space requirements
    • 用于执行执行线程的计算机系统和方法,减少运行时存储空间要求
    • US5765157A
    • 1998-06-09
    • US658501
    • 1996-06-05
    • Timothy G. LindholmWilliam N. Joy
    • Timothy G. LindholmWilliam N. Joy
    • G06F12/02G06F9/44G06F9/46G06F9/48G06F12/06G06F13/00
    • G06F9/4843Y10S707/99942Y10S707/99953
    • A computer system and associated method for executing a plurality of threads of execution with reduced memory space requirements. The computer system comprises a memory, an execution controller, and a data compressor. The execution controller controls execution of the threads such that the threads are executable and unexecutable at different times. The execution controller also stores uncompressed into available space in the run-time memory execution data of the threads when the execution data is generated. The data compressor compresses the uncompressed execution data of compressible ones of the threads that are unexecutable. As a result, space is made available in the run-time memory. The data compressor also decompresses in available space in the run-time memory the compressed execution data of decompressible ones of the threads so that the decompressible ones of the threads may be executed after becoming executable.
    • 一种用于以减少的存储器空间要求执行多个执行线程的计算机系统和相关联的方法。 计算机系统包括存储器,执行控制器和数据压缩器。 执行控制器控制线程的执行,使得线程在不同时间是可执行的和不可执行的。 当生成执行数据时,执行控制器还将未压缩的存储空间存储在线程的运行时存储器执行数据中。 数据压缩器压缩不可执行的可压缩线程的未压缩执行数据。 因此,运行时存储器中提供了空间。 数据压缩器还在运行时存储器中的可用空间中解压缩可解压缩线程的压缩执行数据,使得可解压缩的线程可以在变为可执行之后被执行。
    • 4. 发明授权
    • Locking of computer resources
    • 锁定电脑资源
    • US06725308B2
    • 2004-04-20
    • US10288393
    • 2002-11-05
    • William N. JoyJames Michael O'ConnorMarc Tremblay
    • William N. JoyJames Michael O'ConnorMarc Tremblay
    • G06F946
    • G06F9/52G06F9/3004G06F9/30087
    • A computer processor includes a number of register pairs LOCKADD/LOCKCOUNT to hold values identifying when a computer resource is locked. The LOCKCOUNT register is incremented or decremented in response to lock or unlock instructions, respectively. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. In embodiments without LOCKOUT registers, the lock may be freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header in which two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.
    • 计算机处理器包括多个寄存器对LOCKADD / LOCKCOUNT以保存识别计算机资源何时被锁定的值。 响应锁定或解锁指令,LOCKCOUNT寄存器分别递增或递减。 当与LOCKCOUNT寄存器关联的计数递减为零时,该锁定被释放。 在没有LOCKOUT寄存器的实施例中,锁可以在对应于锁的任何解锁指令上被释放。 在一些实施例中,计算机对象包括头部,其中两个标题LSB存储:(1)指示对象是否被锁定的LOCK位,以及(2)指示线程是否正在等待获取对象的锁的WANT位 。
    • 8. 发明授权
    • Switching method in a multi-threaded processor
    • 多线程处理器中的切换方法
    • US07316021B2
    • 2008-01-01
    • US10779944
    • 2004-02-17
    • William N. JoyMarc TremblayGary LauterbachJoseph I. Chamdani
    • William N. JoyMarc TremblayGary LauterbachJoseph I. Chamdani
    • G06F9/46G06F9/30
    • G06F9/4843G06F9/3842G06F9/3851G06F9/3861
    • A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.
    • 处理器包括用于通过响应于异常情况调用多线程类型功能来执行非线程程序来获得非常快速的异常处理功能的逻辑。 处理器在多线程状态下运行或执行非线程程序时,在执行过程中会经历多个机器状态。 非常快的异常处理逻辑包括将异常信号线连接到线程选择逻辑,导致异常信号引起线程和机器状态的开关。 线程和机器状态的切换使得处理器立即进入并退出异常处理程序,而不用等待排除流水线或队列,并且没有操作系统的软件保存和恢复寄存器的固有时间损失。
    • 10. 发明授权
    • Processor with multiple-thread, vertically-threaded pipeline
    • 处理器采用多线程,垂直螺纹管线
    • US06938147B1
    • 2005-08-30
    • US09309732
    • 1999-05-11
    • William N. JoyMarc TremblayGary LauterbachJoseph I. Chamdani
    • William N. JoyMarc TremblayGary LauterbachJoseph I. Chamdani
    • G06F9/38G06F9/48G06F9/00
    • G06F9/4843G06F9/3851
    • A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.
    • 处理器通过支持和实现垂直多线程和水平多线程来减少由于停滞和空闲而导致的浪费周期时间,并增加执行时间的比例。 垂直多线程允许重叠或“隐藏”高速缓存未命中等待时间。 在垂直多线程中,多个硬件线程共享相同的处理器管道。 在支持多线程的操作系统中,硬件线程通常是进程,轻量级进程,本机线程等。 水平多线程增加了处理器电路结构内的并行性,例如在构成单片处理器的单个集成电路管芯内。 为了在一些处理器实施例中进一步增加系统并行性,在单个管芯中形成多个处理器核。 通过技术进步降低了处理器核心尺寸,从而获得片上多处理器水平线程的进步。