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1. 发明授权

US06725308B2 Locking of computer resources 有权
标题翻译：锁定电脑资源
公开(公告)号：US06725308B2
公开(公告)日：2004-04-20
申请号：US10288393
申请日：2002-11-05
申请人： William N. Joy , James Michael O'Connor , Marc Tremblay
发明人： William N. Joy , James Michael O'Connor , Marc Tremblay
IPC分类号： G06F946
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087
摘要： A computer processor includes a number of register pairs LOCKADD/LOCKCOUNT to hold values identifying when a computer resource is locked. The LOCKCOUNT register is incremented or decremented in response to lock or unlock instructions, respectively. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. In embodiments without LOCKOUT registers, the lock may be freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header in which two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.
摘要翻译：计算机处理器包括多个寄存器对LOCKADD / LOCKCOUNT以保存识别计算机资源何时被锁定的值。响应锁定或解锁指令，LOCKCOUNT寄存器分别递增或递减。当与LOCKCOUNT寄存器关联的计数递减为零时，该锁定被释放。在没有LOCKOUT寄存器的实施例中，锁可以在对应于锁的任何解锁指令上被释放。在一些实施例中，计算机对象包括头部，其中两个标题LSB存储：（1）指示对象是否被锁定的LOCK位，以及（2）指示线程是否正在等待获取对象的锁的WANT位。

2. 发明授权

US6021469A Hardware virtual machine instruction processor 失效
标题翻译：硬件虚拟机指令处理器
公开(公告)号：US6021469A
公开(公告)日：2000-02-01
申请号：US788807
申请日：1997-01-23
申请人： Marc Tremblay , James Michael O'Connor , William N. Joy
发明人： Marc Tremblay , James Michael O'Connor , William N. Joy
IPC分类号： G06F9/30 , G06F9/318 , G06F9/34 , G06F9/345 , G06F9/40 , G06F9/42 , G06F9/445 , G06F9/455 , G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F9/30021 , G06F12/0875 , G06F9/30134 , G06F9/30174 , G06F9/30181 , G06F9/345 , G06F9/3879 , G06F9/4425 , G06F9/443 , G06F9/44589 , G06F9/45504 , G06F2212/451 , Y02B60/1225
摘要： A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. These applications include, for example, an Internet chip for network appliances, a cellular telephone processor, other telecommunications integrated circuits, or other low-power, low-cost applications such as embedded processors, and portable devices.
摘要翻译：硬件虚拟机指令处理器直接执行独立于处理器架构的虚拟机指令。硬件处理器性能高; 成本低廉并具有低功耗。硬件处理器非常适合便携式应用。这些应用包括例如用于网络设备的因特网芯片，蜂窝电话处理器，其他电信集成电路或其他低功耗，低成本的应用，例如嵌入式处理器和便携式设备。

3. 发明授权

US6014723A Processor with accelerated array access bounds checking 失效
标题翻译：具有加速阵列访问限制检查的处理器
公开(公告)号：US6014723A
公开(公告)日：2000-01-11
申请号：US786352
申请日：1997-01-23
申请人： Marc Tremblay , James Michael O'Connor , William N. Joy
发明人： Marc Tremblay , James Michael O'Connor , William N. Joy
IPC分类号： G06F11/28 , G06F9/30 , G06F9/318 , G06F9/345 , G06F9/40 , G06F9/42 , G06F9/445 , G06F9/45 , G06F9/455 , G06F12/08 , G06F12/14 , G06F17/30
CPC分类号： G06F9/30021 , G06F12/0875 , G06F12/1441 , G06F9/264 , G06F9/30134 , G06F9/30174 , G06F9/345 , G06F9/4425 , G06F9/443 , G06F9/44589 , G06F9/45504 , G06F2212/451
摘要： An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that stores and retrieves a plurality of array bound values. Each one of the plurality of array bound values is associated with one of the plurality of array access instructions. An input section simultaneously compares the array access instruction identifier with at least a portion of each of the stored array reference entries, wherein the array access instruction identifier identifies an array access instruction. An output section is configured to provide as an array bounds output values one of the plurality of array bound values stored in one of the plurality of memory locations of the associated memory element. A first comparison element compares the value of the referenced element and the maximum array index boundary value and provides a maximum violation signal if the value of the element is greater than the maximum array size boundary value. A second comparison element compares the value of the element and the minimum array size boundary value and provides a minimum violation signal if the value of the element is less than the minimum array bounds value. Either a maximum violation signal or a minimum violation signal results in an exception.
摘要翻译：阵列边界检查装置被配置为验证信息数组的引用元素在最大数组大小边界值和最小数组大小边界值内。本发明的阵列边界检查装置包括存储和检索多个阵列限定值的关联存储元件。多个阵列绑定值中的每一个与多个阵列访问指令之一相关联。输入部分同时将数组访问指令标识符与每个存储的数组参考条目的至少一部分进行比较，其中数组访问指令标识符标识数组访问指令。输出部分被配置为提供作为阵列限定存储在相关联的存储器元件的多个存储器位置之一中的多个阵列约束值之一的输出值。第一个比较元素比较引用元素的值和最大数组索引边界值，如果元素的值大于最大数组大小边界值，则提供最大违规信号。第二比较元素比较元素的值和最小数组大小边界值，并且如果元素的值小于最小数组边界值，则提供最小违规信号。最大违规信号或最小违规信号都会导致异常。

4. 发明授权

US06529982B2 Locking of computer resources 有权
标题翻译：锁定电脑资源
公开(公告)号：US06529982B2
公开(公告)日：2003-03-04
申请号：US09296705
申请日：1999-04-21
申请人： William N. Joy , James Michael O'Connor , Marc Tremblay
发明人： William N. Joy , James Michael O'Connor , Marc Tremblay
IPC分类号： G06F946
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087
摘要： A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header. Instead, two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.
摘要翻译：计算机处理器包括多个寄存器对LOCKADDR / LOCKCOUNT。在每一对中，LOCKADDR / LOCKCOUNT寄存器将保存标识计算机资源的锁的值。当锁定指令发生时，相应的LOCKCOUNT寄存器增加。当解锁指令发生时，相应的LOCKCOUNT寄存器递减。当与LOCKCOUNT寄存器关联的计数递减为零时，该锁定被释放。该方案在许多频繁发生的情况下提供快速锁定和解锁。在一些实施例中，省略LOCKCOUNT寄存器，并且在与锁相对应的任何解锁指令上释放锁。在一些实施例中，计算机对象包括包括指向类结构的指针的报头。类结构在4字节边界上对齐，因此指向类结构的指针的两个LSB为零，不存储在标题中。相反，两个标题LSB存储：（1）指示对象是否被锁定的LOCK位，以及（2）指示线程是否正在等待获取对象的锁的WANT位。

5. 发明授权

US5968157A Locking of computer resources 失效
公开(公告)号：US5968157A
公开(公告)日：1999-10-19
申请号：US788808
申请日：1997-01-23
申请人： William N. Joy , James Michael O'Connor , Marc Tremblay
发明人： William N. Joy , James Michael O'Connor , Marc Tremblay
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087
摘要： A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header. Instead, two header LSBs store: (1) a LOCK bit indicating whether the object is locked, and (2) a WANT bit indicating whether a thread is waiting to acquire a lock for the object.

6. 发明授权

US06694347B2 Switching method in a multi-threaded processor 有权
公开(公告)号：US06694347B2
公开(公告)日：2004-02-17
申请号：US10074419
申请日：2002-02-12
申请人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
发明人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.

7. 发明授权

US06507862B1 Switching method in a multi-threaded processor 有权
公开(公告)号：US06507862B1
公开(公告)日：2003-01-14
申请号：US09309735
申请日：1999-05-11
申请人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
发明人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
IPC分类号： G06F946
CPC分类号： G06F9/4843 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.

8. 发明授权

US07316021B2 Switching method in a multi-threaded processor 有权
标题翻译：多线程处理器中的切换方法
公开(公告)号：US07316021B2
公开(公告)日：2008-01-01
申请号：US10779944
申请日：2004-02-17
申请人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
发明人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
IPC分类号： G06F9/46 , G06F9/30
CPC分类号： G06F9/4843 , G06F9/3842 , G06F9/3851 , G06F9/3861
摘要： A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.
摘要翻译：处理器包括用于通过响应于异常情况调用多线程类型功能来执行非线程程序来获得非常快速的异常处理功能的逻辑。处理器在多线程状态下运行或执行非线程程序时，在执行过程中会经历多个机器状态。非常快的异常处理逻辑包括将异常信号线连接到线程选择逻辑，导致异常信号引起线程和机器状态的开关。线程和机器状态的切换使得处理器立即进入并退出异常处理程序，而不用等待排除流水线或队列，并且没有操作系统的软件保存和恢复寄存器的固有时间损失。

9. 发明授权

US06938147B1 Processor with multiple-thread, vertically-threaded pipeline 有权
标题翻译：处理器采用多线程，垂直螺纹管线
公开(公告)号：US06938147B1
公开(公告)日：2005-08-30
申请号：US09309732
申请日：1999-05-11
申请人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
发明人： William N. Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
IPC分类号： G06F9/38 , G06F9/48 , G06F9/00
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.
摘要翻译：处理器通过支持和实现垂直多线程和水平多线程来减少由于停滞和空闲而导致的浪费周期时间，并增加执行时间的比例。垂直多线程允许重叠或“隐藏”高速缓存未命中等待时间。在垂直多线程中，多个硬件线程共享相同的处理器管道。在支持多线程的操作系统中，硬件线程通常是进程，轻量级进程，本机线程等。水平多线程增加了处理器电路结构内的并行性，例如在构成单片处理器的单个集成电路管芯内。为了在一些处理器实施例中进一步增加系统并行性，在单个管芯中形成多个处理器核。通过技术进步降低了处理器核心尺寸，从而获得片上多处理器水平线程的进步。

10. 发明授权

US06405300B1 Combining results of selectively executed remaining sub-instructions with that of emulated sub-instruction causing exception in VLIW processor 有权
标题翻译：将选择执行的剩余子指令的结果与在VLIW处理器中引起异常的仿真子指令的结果相结合
公开(公告)号：US06405300B1
公开(公告)日：2002-06-11
申请号：US09273602
申请日：1999-03-22
申请人： Marc Tremblay , William N. Joy
发明人： Marc Tremblay , William N. Joy
IPC分类号： G06F944
CPC分类号： G06F9/3017 , G06F9/30101 , G06F9/3853 , G06F9/3861 , G06F9/3885
摘要： One embodiment of the present invention provides a system that efficiently emulates sub-instructions in a very long instruction word (VLIW) processor. The system operates by receiving an exception condition during execution of a VLIW instruction within a VLIW program. This exception condition indicates that at least one sub-instruction within the VLIW instruction requires emulation in software or software assistance. In processing this exception condition, the system emulates the sub-instructions that require emulation in software and stores the results. The system also selectively executes in hardware any remaining sub-instructions in the VLIW instruction that do not require emulation in software. The system finally combines the results from the sub-instructions emulated in software with the results from the remaining sub-instructions executed in hardware, and resumes execution of the VLIW program.
摘要翻译：本发明的一个实施例提供了一种在非常长的指令字（VLIW）处理器中有效地模拟子指令的系统。该系统通过在VLIW程序中执行VLIW指令期间接收到异常情况来进行操作。该异常条件表示VLIW指令中的至少一个子指令需要软件或软件协助进行仿真。在处理此异常情况时，系统会模拟需要软件仿真并存储结果的子指令。该系统还在硬件中选择性地执行VLIW指令中的任何剩余子指令，这些指令不需要软件仿真。系统最终将从软件中仿真的子指令的结果与硬件中执行的剩余子指令的结果相结合，并恢复VLIW程序的执行。

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