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1. 发明授权

US06228208B1 Plasma density and etch rate enhancing semiconductor processing chamber 失效
标题翻译：等离子体密度和蚀刻速率增强半导体处理室
公开(公告)号：US06228208B1
公开(公告)日：2001-05-08
申请号：US09133279
申请日：1998-08-12
申请人： Thorsten Lill , Alan Ouye
发明人： Thorsten Lill , Alan Ouye
IPC分类号： C23F102
CPC分类号： H01J37/32458
摘要： A lid assembly for a narrow-gap magnetically enhanced reactive ion etch (MERIE) chamber. The lid assembly has a lid and a liner. Both pieces are substantially U-shaped and interfit such that the interface between them extends outside the chamber. A blocker plate is situated in a recess between a lower surface of the lid and an upper surface of the liner. The blocker plate is concave in shape so that a downward bow of the lid does not exert a stress on the blocker plate. The novel lid assembly is more leak resistant, requires less cleaning time and is cheaper than a design that utilizes a moving pedestal.
摘要翻译：用于窄间隙磁性增强反应离子蚀刻（MERIE）室的盖组件。盖组件具有盖和衬垫。两个部件基本上是U形的并且互相配合使得它们之间的界面延伸到室外。阻挡板位于盖的下表面和衬垫的上表面之间的凹部中。阻挡板的形状是凹形的，使得盖的向下弓不会在阻挡板上施加应力。新颖的盖组件更具防漏性，需要较少的清洁时间，并且比使用移动底座的设计便宜。

2. 发明申请

US20080197109A1 Etch pattern definition using a CVD organic layer as an anti-reflection coating and hardmask 审中-公开
标题翻译：使用CVD有机层作为防反射涂层和硬掩模的蚀刻图案定义
公开(公告)号：US20080197109A1
公开(公告)日：2008-08-21
申请号：US11981930
申请日：2007-10-31
申请人： David S. Mui , Wei Liu , Thorsten Lill , Christopher Dennis Bencher , Yuxiang May Wang
发明人： David S. Mui , Wei Liu , Thorsten Lill , Christopher Dennis Bencher , Yuxiang May Wang
IPC分类号： C23F1/00
CPC分类号： H01L21/0276 , H01L21/28035 , H01L21/3081 , H01L21/3088 , H01L21/31138 , H01L21/3146 , H01L21/32137 , H01L21/32139
摘要： A multilayer antireflective hard mask structure is disclosed. The structure comprises: (a) a CVD organic layer, wherein the CVD organic layer comprises carbon and hydrogen; and (b) a dielectric layer over the CVD organic layer. The dielectric layer is preferably a silicon oxynitride layer, while the CVD organic layer preferably comprises 70-80% carbon, 10-20% hydrogen and 5-15% nitrogen. Also disclosed are methods of forming and trimming such a multilayer antireflective hard mask structure. Further disclosed are methods of etching a substrate structure using a mask structure that contains a CVD organic layer and optionally has a dielectric layer over the CVD organic layer.
摘要翻译：公开了一种多层抗反射硬掩模结构。该结构包括：（a）CVD有机层，其中CVD有机层包含碳和氢; 和（b）CVD有机层上的电介质层。电介质层优选为氮氧化硅层，而CVD有机层优选包含70-80％的碳，10-20％的氢和5-15％的氮。还公开了形成和修整这种多层抗反射硬掩模结构的方法。还公开了使用包含CVD有机层并且可选地在CVD有机层上具有介电层的掩模结构来蚀刻衬底结构的方法。

3. 发明申请

US20080099040A1 INTEGRATED METHOD FOR REMOVAL OF HALOGEN RESIDUES FROM ETCHED SUBSTRATES IN A PROCESSING SYSTEM 有权
标题翻译：用于从加工系统中的蚀刻基板去除卤素残留物的综合方法
公开(公告)号：US20080099040A1
公开(公告)日：2008-05-01
申请号：US11676161
申请日：2007-02-16
申请人： Kenneth J. Bahng , Matthew Fenton Davis , Thorsten Lill , Steven H. Kim
发明人： Kenneth J. Bahng , Matthew Fenton Davis , Thorsten Lill , Steven H. Kim
IPC分类号： C25F3/00 , B08B7/00
CPC分类号： H01L21/02071 , H01L21/02057 , H01L21/67115 , Y10S414/135 , Y10S438/906 , Y10S438/963
摘要： A method and system for removing volatile residues from a substrate are provided. In one embodiment, the volatile residues removal process is performed en-routed in the system while performing a halogen treatment process on the substrate. The volatile residues removal process is performed in the system other than the halogen treatment processing chamber and a FOUP. In one embodiment, a method for volatile residues from a substrate includes providing a processing system having a vacuum tight platform, processing a substrate in a processing chamber of the platform with a chemistry comprising halogen, and treating the processed substrate in the platform to release volatile residues from the treated substrate.
摘要翻译：提供了用于从基板去除挥发性残留物的方法和系统。在一个实施方案中，挥发性残余物去除过程在系统中进行，同时在衬底上进行卤素处理过程。在除卤素处理室和FOUP以外的系统中进行挥发性残渣去除处理。在一个实施方案中，用于来自基材的挥发性残余物的方法包括提供具有真空密封平台的处理系统，在平台的处理室中处理基材，其中包含卤素的化学物质，以及处理所述平台中的经处理的基材以释放挥发性来自处理过的底物的残留物。

4. 发明授权

US07067432B2 Methodology for in-situ and real-time chamber condition monitoring and process recovery during plasma processing 失效
标题翻译：等离子体处理过程中原位和实时室状态监测和过程恢复方法
公开(公告)号：US07067432B2
公开(公告)日：2006-06-27
申请号：US10608670
申请日：2003-06-26
申请人： Songlin Xu , Thorsten Lill
发明人： Songlin Xu , Thorsten Lill
IPC分类号： H01L21/302
CPC分类号： H01J37/32862 , G01N21/68 , H01J37/32935 , H01J37/32972
摘要： A new methodology of monitoring process drift and chamber seasoning is presented based on the discovery of the strong correlation between chamber surface condition and free radical density in a plasma. Lower free radical density indicates either there is a significant process drift in the case of production wafer etching or that the chamber needs more seasoning before resuming production wafer etching. Free radical density in the plasma is monitored through measuring the emission intensities of free radicals in the plasma by an optical spectrometer. A timely detection of the extent of process drift and chamber seasoning can help to minimize the chamber downtime and improve its throughput significantly. Such method can also be implemented in existing production wafer etching or chamber seasoning practices in an in-situ, real-time, and non-intrusive manner.
摘要翻译：基于发现等离子体中室表面状态与自由基密度之间的强相关性，提出了监测过程漂移和室内调节的新方法。较低的自由基密度表示在生产晶片蚀刻的情况下存在显着的工艺漂移，或者在恢复生产晶片蚀刻之前，室需要更多的调味。通过光谱仪测量等离子体中自由基的发射强度来监测等离子体中的自由基密度。及时检测过程漂移和室内调节的程度可以帮助最大限度地减少室内停机时间，并显着提高其产量。这种方法也可以以现场，实时和非侵入的方式在现有的生产晶片蚀刻或室调节实践中实现。

5. 发明申请

US20060032833A1 Encapsulation of post-etch halogenic residue 审中-公开
标题翻译：蚀刻后的卤素残留物的封装
公开(公告)号：US20060032833A1
公开(公告)日：2006-02-16
申请号：US10915519
申请日：2004-08-10
申请人： Mark Kawaguchi , Thorsten Lill , Anisul Khan
发明人： Mark Kawaguchi , Thorsten Lill , Anisul Khan
IPC分类号： B44C1/22
CPC分类号： H01L21/0206 , H01L21/02063 , H01L21/02071 , H01L21/32136
摘要： A method of etching is provided that includes transferring a substrate into a vacuum environment, etching a material layer on the substrate and depositing a polymeric film encapsulating etch residues on the substrate without removing the substrate from the vacuum environment.
摘要翻译：提供了一种蚀刻方法，其包括将衬底转移到真空环境中，蚀刻衬底上的材料层并且在衬底上沉积封装蚀刻残留物的聚合物膜，而不从真空环境中移除衬底。

6. 发明授权

US06827869B2 Method of micromachining a multi-part cavity 失效
标题翻译：微加工多部分腔体的方法
公开(公告)号：US06827869B2
公开(公告)日：2004-12-07
申请号：US10194167
申请日：2002-07-11
申请人： Dragan Podlesnik , Thorsten Lill , Jeff Chinn , Shaoher X. Pan , Anisul Khan , Maocheng Li , Yiqiong Wang
发明人： Dragan Podlesnik , Thorsten Lill , Jeff Chinn , Shaoher X. Pan , Anisul Khan , Maocheng Li , Yiqiong Wang
IPC分类号： H01L21302
CPC分类号： H01L27/1087 , B81B2201/052 , B81B2203/0315 , B81B2203/033 , B81C1/00119 , B81C2201/016 , H01L21/3065 , H01L21/3086
摘要： The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes. The method is also useful whenever it is necessary to maintain tight control over the dimensions of the shaped opening.
摘要翻译：本公开涉及我们发现用于蚀刻衬底中的多部分空腔的特别有效的方法。该方法提供了首先蚀刻成形开口，在成形开口的内表面的至少一部分上沉积保护层，然后直接在成形开口下面蚀刻成形腔，并与成形开口连续连通。保护层在蚀刻成形腔体期间保护成形开口的蚀刻轮廓，从而如果需要，成形开口和成形腔体可以被蚀刻以具有不同的形状。在本发明方法的特定实施例中，横向蚀刻阻挡层和/或注入的蚀刻停止点也用于引导蚀刻工艺。本发明的方法可以应用于需要或期望提供具有不同形状的成形开口和下面的成形腔的任何应用。只要需要对成形开口的尺寸进行严格控制，该方法也是有用的。

7. 发明授权

US06660127B2 Apparatus for plasma etching at a constant etch rate 失效
标题翻译：用于以恒定蚀刻速率等离子体蚀刻的装置
公开(公告)号：US06660127B2
公开(公告)日：2003-12-09
申请号：US10075223
申请日：2002-02-12
申请人： Padmapani Nallan , John Holland , Valentin Todorov , Thorsten Lill
发明人： Padmapani Nallan , John Holland , Valentin Todorov , Thorsten Lill
IPC分类号： C23C1600
CPC分类号： H01J37/321
摘要： We have discovered a method which permits plasma etching at a constant etch rate. The constant etch rate is achieved by controlling plasma process parameters so that a stable plasma is obtained, with a portion of the power deposited to the plasma being a capacitive contribution, and a portion being an inductive contribution. In particular, a stable plasma may be obtained within two process regions. In the first region, the gradient of the capacitive power to the power applied to the inductively coupled source for plasma generation [∂Pcap/∂PRF] is greater than 0. In the second region, plasma stability is controlled so that [∂Pcap/∂PRF] is less than 0 and so that Pcap
摘要翻译：我们已经发现了以恒定的蚀刻速率允许等离子体蚀刻的方法。通过控制等离子体工艺参数来实现恒定的蚀刻速率，从而获得稳定的等离子体，其中沉积到等离子体的功率的一部分是电容性贡献，并且部分是归纳贡献。特别地，可以在两个工艺区域内获得稳定的等离子体。在第一区域中，电容性功率对施加到用于等离子体产生的电感耦合源的功率的梯度大于0.在第二区域中，等离子体稳定性受到控制，使得[∂Pcap/ ∠PRF]小于0，因此Pcap << PRF。通常，Pcap的幅度小于PRF大小的10％。在稳定等离子体区域中的蚀刻工艺的操作使得能够使用定时蚀刻终点。

8. 发明授权

US06613682B1 Method for in situ removal of a dielectric antireflective coating during a gate etch process 失效
标题翻译：在栅极蚀刻工艺期间原位去除介电抗反射涂层的方法
公开(公告)号：US06613682B1
公开(公告)日：2003-09-02
申请号：US09422816
申请日：1999-10-21
申请人： Mohit Jain , Thorsten Lill , Jeff Chinn
发明人： Mohit Jain , Thorsten Lill , Jeff Chinn
IPC分类号： H01L21302
CPC分类号： H01L21/0276 , H01L21/28123 , H01L21/31116 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： The present invention provides a method for the simultaneous removal of an oxygen and/or nitrogen-containing dielectric antireflective coating (“DARC”) during plasma etching of an underlying layer in a film stack. According to the method of the invention, the film stack is etched using a plasma containing reactive fluorine species. The concentration of reactive fluorine species within the plasma is controlled based on one or more of the following factors: the oxygen content of the antireflective coating, the nitrogen content of the antireflective coating, the thickness of the antireflection coating layer, and the thickness of the underlying film stack layer. The disclosure of the invention provides preferred combinations of plasma source gases which provide for the simultaneous removal of an oxygen and/or nitrogen-containing DARC layer during etching of an underlying etch stack layer, where the underlying stack layer comprises a metal silicide, polysilicon, or a metal. Also provided herein is a formula for determining the total amount of DARC removed using a given etch process recipe, based on the etch selectivity of the particular process recipe
摘要翻译：本发明提供了一种用于在膜堆叠中的下层的等离子体蚀刻期间同时去除氧和/或含氮介电抗反射涂层（“DARC”）的方法。根据本发明的方法，使用含有反应性氟物质的等离子体来蚀刻膜堆叠。基于以下一个或多个因素来控制等离子体中的活性氟物质的浓度：抗反射涂层的氧含量，抗反射涂层的氮含量，抗反射涂层的厚度和抗反射涂层的厚度底层薄膜堆叠层。本发明的公开内容提供了等离子体源气体的优选组合，其提供了在蚀刻下面的蚀刻堆叠层期间同时去除氧和/或含氮DARC层，其中下面的堆叠层包括金属硅化物，多晶硅，或金属。本文还提供了基于特定工艺配方的蚀刻选择性来确定使用给定蚀刻工艺配方去除的DARC的总量的公式

9. 发明授权

US06518190B1 Plasma reactor with dry clean apparatus and method 失效
标题翻译：具有干洗装置和方法的等离子体反应器
公开(公告)号：US06518190B1
公开(公告)日：2003-02-11
申请号：US09470560
申请日：1999-12-23
申请人： Thorsten Lill , Jeffrey D. Chinn
发明人： Thorsten Lill , Jeffrey D. Chinn
IPC分类号： H01L2100
CPC分类号： H01J37/32862 , H01J37/321
摘要： A preferred embodiment of the plasma reactor of the present invention provides a chamber adapted to process a workpiece having at least one wall capable of allowing inductive power coupling into the reactor chamber. A source power antenna, capable of generating a processing plasma, confronts a portion of the at least one wall. A dry clean antenna is located adjacent the chamber beside a portion of the at least one wall not confronted by the source power antenna. During workpiece processing, the dry clean antenna preferably has essentially a floating potential. After workpiece processing has ceased, a dry clean plasma may be generated by inductive coupling using the dry clean antenna. Embodiments of the present invention allow dry clean plasma characteristics to be optimized to improve dry clean effectiveness. The source power antenna also may couple power to the dry clean plasma, preferably in parallel with the dry clean antenna. With such embodiments, the source power antenna may be operated so that it couples less power to the dry clean plasma, while the dry clean antenna couples more. This allows sputtering of the chamber wall under the source power antenna to be reduced and allows more effective removal of accumulated deposits.
摘要翻译：本发明的等离子体反应器的一个优选实施例提供了适于处理工件的室，该工件具有至少一个能够将感应功率耦合到反应器室中的壁。能够产生处理等离子体的源功率天线面对至少一个壁的一部分。干净的天线位于与源功率天线不相对的至少一个壁的一部分旁边的室附近。在工件加工过程中，干式天线优选具有基本的浮动电位。在工件处理停止之后，可以通过使用干式天线的电感耦合来产生干净的等离子体。本发明的实施例允许优化干洗等离子体特性以改善干洗效果。源功率天线还可以将功率耦合到干洗等离子体，优选地与干净的天线并联。通过这样的实施例，源功率天线可以被操作，使得它将更少的功率耦合到干净的等离子体，而干净的天线更多耦合。这允许在源功率天线下方的室壁的溅射被减少并且允许更有效地去除积累的沉积物。

10. 发明授权

US06284665B1 Method for controlling the shape of the etch front in the etching of polysilicon 失效
公开(公告)号：US06284665B1
公开(公告)日：2001-09-04
申请号：US09465951
申请日：1999-12-17
申请人： Thorsten Lill , Michael Grimbergen
发明人： Thorsten Lill , Michael Grimbergen
IPC分类号： H01L213065
CPC分类号： H01L27/10861 , H01L21/32137 , H01L21/763 , H01L29/66181
摘要： The present disclosure pertains to our discovery that the use of a particular combination of etchant gases results in the formation of a substantially flat etch front for polysilicon etching applications. In general, the process of the invention is useful for controlling the shape 104 of the etch front during the etchback of polysilicon. Typically, the process comprises isotropically etching the polysilicon using a plasma produced from a plasma source gas comprising a particular combination of reactive species which selectively etch polysilicon. The plasma source gas comprises from about 80% to about 95% by volume of a fluorine-comprising gas, and from about 5% to about 20% by volume of an additive gas selected from a group consisting of a bromine-comprising gas, a chlorine-comprising gas, an iodine-comprising gas, or a combination thereof. A preferred method of the invention, used to perform recess etchback of a polysilicon-filled trench in a substrate, comprises the following steps: a) providing a trench formed in a semiconductor structure, wherein the structure includes a substrate, at least one gate dielectric layer overlying a surface of the substrate, and at least one etch barrier layer overlying the gate dielectric layer; b) forming a conformal dielectric film overlying the etch barrier layer and the sidewall and bottom of the trench; c) filling the trench with a layer of polysilicon which overlies the conformal dielectric film; and d) isotropically etching the polysilicon back to a predetermined depth within the trench using a plasma produced from a plasma source gas comprising a reactive species which selectively etches polysilicon, wherein the plasma source gas comprises from about 80% to about 95% by volume of a fluorine-comprising gas, and from about 5% to about 20% by volume of an additive gas selected from a group consisting of a bromine-comprising gas, a chlorine-comprising gas, an iodine-comprising gas, or a combination thereof. Also disclosed herein is a method of forming a trench capacitor in a single-crystal silicon substrate, the trench capacitor including a dielectric collar and a buried strap.

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