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1. 发明授权

US6055722A Stripline flexible cable to printed circuit board attachment system 失效
标题翻译：带状柔性电缆到印刷电路板附件系统
公开(公告)号：US6055722A
公开(公告)日：2000-05-02
申请号：US81925
申请日：1998-05-20
申请人： Thomas S. Tighe , Gershon Akerling
发明人： Thomas S. Tighe , Gershon Akerling
IPC分类号： H01R12/62 , H05K1/02 , H05K3/36 , H05K9/00 , H05K9/06
CPC分类号： H01R12/62 , H05K3/363 , H05K9/0039 , H05K1/0237 , H05K2201/0715 , H05K2201/0919 , H05K2201/09354 , H05K2203/0195 , Y10T29/49142 , Y10T29/49147 , Y10T29/49149
摘要： Shielded stripline multi-lead flex cable is successfully attached to solder pads on a circuit board by applying a hot bar to the backside of the cable placed in abuttment with the associated solder pads. The hot bar generates sufficient heat to reflow pretinned cable elements and the corresponding solder pads of the circuit board. An attachment is attained in which the outer ground plane metal layer of the cable covers the signal lines and the other ground plane metal layer is attached adjacent those signal lines, producing effective RF shielding of the signal leads and minimizing introduction of inductance into the ground current circuit. A novel cable end configuration and cable termination is disclosed to implement the attaching procedure.
摘要翻译：屏蔽带状线多引线柔性电缆通过将热棒施加到与相关联的焊盘邻接的电缆的背面而成功地附接到电路板上的焊盘。热条产生足够的热量以回流预先镀的电缆元件和电路板的相应焊盘。实现了附接，其中电缆的外接地平面金属层覆盖信号线，并且另一接地平面金属层附接在这些信号线附近，产生信号引线的有效RF屏蔽并最小化将电感引入接地电流电路。公开了一种新颖的电缆端配置和电缆终端来实现附接过程。

2. 发明授权

US5924875A Cryogenic flex cable connector 失效
公开(公告)号：US5924875A
公开(公告)日：1999-07-20
申请号：US886312
申请日：1997-07-01
申请人： Thomas S. Tighe , Gershon Akerling
发明人： Thomas S. Tighe , Gershon Akerling
IPC分类号： H01R12/61 , H01R13/24 , H05K3/36 , H01R9/09
CPC分类号： H05K3/365 , H01R12/774 , H01R12/78 , H01R13/2478 , Y10T29/49126 , Y10T29/49149 , Y10T29/49213
摘要： A new electrical connector system employs two printed circuit board type connector components (1 & 3), each containing a plurality of plated-on metal lines (11 & 13) running along the board in parallel, and a replaceable contact element (9), termed an interposer, that is sandwiched between those printed circuit boards. The interposer contains malleable electrical contacts (15 & 17) on each side that extend electrically from one surface to the other and serves as a contact bridge for those connector contacts. The interposer is formed as a thin insulator strip and metal bumps on the top and bottom sides of the strip serve as the electrical contacts. Bridging connection for metal bumps on the top side with associated bumps on the bottom side is served with plated-through holes (16). The metal bumps are of Indium and Tin that is covered by a flash of Gold. Ancillary to the described connector, a new method for constructing an electrical connector is also presented.

3. 发明授权

US6146912A Method for parallel alignment of a chip to substrate 有权
标题翻译：芯片与衬底平行排列的方法
公开(公告)号：US6146912A
公开(公告)日：2000-11-14
申请号：US309945
申请日：1999-05-11
申请人： Thomas S. Tighe , Gershon Akerling
发明人： Thomas S. Tighe , Gershon Akerling
IPC分类号： H01L21/00 , H01L21/68 , H01L21/66 , G01R31/26
CPC分类号： H01L21/6835 , H01L21/67144 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/75 , H01L2224/75302 , H01L2224/75745 , H01L2224/75823 , H01L2924/00014 , H01L2924/01079
摘要： A method and apparatus for bonding a chip to a substrate is described, wherein the apparatus includes a chip holder assembly comprising an outer holder having a cavity formed therein and an inner holder for holding the chip, and by releaseably securing the inner holder within the outer holder cavity and contacting the chip to the substrate the inner holder has selective angular rotation within the cavity to make parallel the chip and the substrate.
摘要翻译：描述了一种用于将芯片接合到基板的方法和装置，其中该装置包括一个芯片保持器组件，该芯片保持器组件包括形成在其中的腔体的外部保持器和用于保持芯片的内部保持器，并且通过将内部保持器可释放地固定在外部保持器腔并将芯片接触到衬底，内部保持器在空腔内具有选择性的角度旋转以使芯片和衬底平行。

4. 发明授权

US5970608A Cryogenic flex cable connector 失效
标题翻译：低温柔性电缆连接器
公开(公告)号：US5970608A
公开(公告)日：1999-10-26
申请号：US174953
申请日：1998-10-19
申请人： Thomas S. Tighe , Gershon Akerling
发明人： Thomas S. Tighe , Gershon Akerling
IPC分类号： H01R12/61 , H01R13/24 , H05K3/36 , H01R43/02
CPC分类号： H05K3/365 , H01R12/774 , H01R12/78 , H01R13/2478 , Y10T29/49126 , Y10T29/49149 , Y10T29/49213
摘要： A new electrical connector system employs two printed circuit board type connector components (1 & 3), each containing a plurality of plated-on metal lines (11 & 13) running along the board in parallel, and a replaceable contact element (9), termed an interposer, that is sandwiched between those printed circuit boards. The interposer contains malleable electrical contacts (15 & 17) on each side that extend electrically from one surface to the other and serves as a contact bridge for those connector contacts. The interposer is formed as a thin insulator strip and metal bumps on the top and bottom sides of the strip serve as the electrical contacts. Bridging connection for metal bumps on the top side with associated bumps on the bottom side is served with plated-through holes (16). The metal bumps are of Indium and Tin that is covered by a flash of Gold. Ancillary to the described connector, a new method for constructing an electrical connector is also presented.
摘要翻译：新的电连接器系统采用两个印刷电路板型连接器部件（1和3），每个印刷电路板型连接器部件（1和3）均包含沿板平行延伸的多个镀金属线（11和13）和可更换的接触元件（9）称为插入器，夹在这些印刷电路板之间。插入器包含在每个侧面上延伸的电触点（15和17），其从一个表面电连接到另一个表面，并且用作这些连接器触点的接触桥。该插入件形成为薄的绝缘条，并且在该带的顶部和底部上的金属凸块用作电触点。上侧的金属凸块的桥接连接与底侧相关的凸点配有电镀通孔（16）。金属凸块是由金和闪光覆盖的铟和锡。附带说明的连接器，还提出了一种用于构建电连接器的新方法。

5. 发明申请

US20120152454A1 LOW MASS FOAM ELECTRICAL STRUCTURE 有权
标题翻译：低质量泡沫电结构
公开(公告)号：US20120152454A1
公开(公告)日：2012-06-21
申请号：US13315590
申请日：2011-12-09
申请人： Steven J. Mass , Anthony L. Long , Mansoor K. Siddiqui , Marijan D. Grgas , Gershon Akerling
发明人： Steven J. Mass , Anthony L. Long , Mansoor K. Siddiqui , Marijan D. Grgas , Gershon Akerling
IPC分类号： G02B6/10 , B22D19/00 , B32B38/08 , B29C70/00 , H01L23/06 , H05K7/20
CPC分类号： H01P11/006 , H01P3/06 , H01P3/087 , H01P3/121 , H01P11/001
摘要： An electrical structure having a foam housing is set forth. The foam housing includes an interior surface forming a conductive cavity adapted to carry energized waveforms therethrough. An electrical component of the electrical structure is integrally formed with the interior surface as the foam housing of the structure is assembled.
摘要翻译：阐述了具有泡沫壳体的电气结构。泡沫壳体包括形成适于承载通电波形的导电腔的内表面。当结构的泡沫壳体组装时，电气结构的电气部件与内表面一体形成。

6. 发明授权

US07135779B2 Method for packaging integrated circuit chips 有权
标题翻译：集成电路芯片封装方法
公开(公告)号：US07135779B2
公开(公告)日：2006-11-14
申请号：US10823877
申请日：2004-04-14
申请人： James Anderson , Gershon Akerling
发明人： James Anderson , Gershon Akerling
IPC分类号： H01L23/48
CPC分类号： H01L24/49 , H01L23/3114 , H01L23/481 , H01L23/482 , H01L24/48 , H01L25/105 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/4911 , H01L2224/73265 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/15313 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/00 , H01L2924/00015 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A method for packaging integrated circuits in a wafer format that eliminates wire bonds. A wafer substrate on which the integrated circuits have been fabricated is patterned and etched to form signal and ground via through the substrate. A back-side ground plane is deposited in contact with the ground vias. A protective layer is formed on the top surface of the substrate, and a protective layer is formed on the bottom surface of the substrate, where the bottom protective layer fills in removed substrate material between the integrated circuits. Vias are formed through the bottom protective layer, and the wafer substrate is diced between the integrated circuits.
摘要翻译：一种以晶圆格式封装集成电路的方法，其消除引线键合。已经在其上制造集成电路的晶片基板被图案化和蚀刻以通过基板形成信号和接地。背面接地平面与地面通孔相接触。在衬底的顶表面上形成保护层，并且在衬底的底表面上形成保护层，其中底部保护层填充在集成电路之间的去除的衬底材料中。通过底部保护层形成通孔，并且在集成电路之间切割晶片衬底。

7. 发明授权

US09293800B2 RF transmission line disposed within a conductively plated cavity located in a low mass foam housing 有权
标题翻译： RF传输线设置在位于低质量泡沫壳体内的导电电镀腔内
公开(公告)号：US09293800B2
公开(公告)日：2016-03-22
申请号：US13315590
申请日：2011-12-09
申请人： Steven J. Mass , Anthony L. Long , Mansoor K. Siddiqui , Marijan D. Grgas , Gershon Akerling
发明人： Steven J. Mass , Anthony L. Long , Mansoor K. Siddiqui , Marijan D. Grgas , Gershon Akerling
IPC分类号： H01P3/08 , H01P3/06 , H01P3/12 , H01P11/00
CPC分类号： H01P11/006 , H01P3/06 , H01P3/087 , H01P3/121 , H01P11/001
摘要： An electrical structure having a foam housing is set forth. The foam housing includes an interior surface forming a conductive cavity adapted to carry energized waveforms therethrough. An electrical component of the electrical structure is integrally formed with the interior surface as the foam housing of the structure is assembled.
摘要翻译：阐述了具有泡沫壳体的电气结构。泡沫壳体包括形成适于承载通电波形的导电腔的内表面。当结构的泡沫壳体组装时，电气结构的电气部件与内表面一体地形成。

8. 发明授权

US6050476A Reworkable microelectronic multi-chip module 失效
公开(公告)号：US6050476A
公开(公告)日：2000-04-18
申请号：US156452
申请日：1998-09-19
申请人： Karen E. Yokoyama , Gershon Akerling
发明人： Karen E. Yokoyama , Gershon Akerling
IPC分类号： B23K20/00 , H01L21/48 , H01L21/60 , H01L21/603 , H01L21/66 , H01L23/538
CPC分类号： H01L23/5382 , H01L21/485 , H01L22/20 , H01L24/75 , H01L2224/13109 , H01L2224/16 , H01L2224/81193 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01049 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/30107
摘要： A reworkable cold welded microelectronic multi-chip module contains cold welded microelectronic chips in which the chip's cold weld metal bonding pads (3) are constructed of a metal having one hardness and the corresponding cold weld metal bonding pads of the multi-chip module's substrate (5) are of a different greater hardness, which, despite the difference in hardness, cold weld to one another. Two forms of Indium preferably serve as the metals. If for any reason the chip must be removed from the module, it is found that the cold weld breaks at a predictable location. A new microelectronic chip may thereby be cold welded to the module substrate as a replacement. New rework and testing procedures are thereby made possible.

9. 发明授权

US5920464A Reworkable microelectronic multi-chip module 失效
公开(公告)号：US5920464A
公开(公告)日：1999-07-06
申请号：US935267
申请日：1997-09-22
申请人： Karen E. Yokoyama , Gershon Akerling
发明人： Karen E. Yokoyama , Gershon Akerling
IPC分类号： B23K20/00 , H01L21/48 , H01L21/60 , H01L21/603 , H01L21/66 , H01L23/538 , H05K1/11 , B23K20/12 , H05K1/14
CPC分类号： H01L23/5382 , H01L21/485 , H01L22/20 , H01L24/75 , H01L2224/13109 , H01L2224/16 , H01L2224/81193 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01049 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/30107
摘要： A reworkable cold welded microelectronic multi-chip module contains cold welded microelectronic chips in which the chip's cold weld metal bonding pads (3) are constructed of a metal having one hardness and the corresponding cold weld metal bonding pads of the multi-chip module's substrate (5) are of a different greater hardness, which, despite the difference in hardness, cold weld to one another. Two forms of Indium preferably serve as the metals. If for any reason the chip must be removed from the module, it is found that the cold weld breaks at a predictable location. A new microelectronic chip may thereby be cold welded to the module substrate as a replacement. New rework and testing procedures are thereby made possible.

10. 发明授权

US06936913B2 High performance vias for vertical IC packaging 有权
标题翻译：用于垂直IC封装的高性能通孔
公开(公告)号：US06936913B2
公开(公告)日：2005-08-30
申请号：US10317680
申请日：2002-12-11
申请人： Gershon Akerling , James M. Anderson , Eric L. Upton
发明人： Gershon Akerling , James M. Anderson , Eric L. Upton
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L23/48 , H01L25/065 , H01L25/07 , H01L25/18 , H01L23/02
CPC分类号： H01L23/481 , H01L25/0657 , H01L2224/05573 , H01L2224/056 , H01L2224/16147 , H01L2224/16237 , H01L2224/81141 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014
摘要： A semiconductor device, a microelectromechanical system package and a method of making the same utilize high performance vias for vertical IC packaging. A semiconductor die of the device/package has a substrate with integrated circuitry formed on a front side of the substrate. A metal bonding pad overlies the substrate on the front side of the substrate and is electrically connected to the integrated circuitry. A solder bump is located on the metal bonding pad. An electrically conductive via extends through the substrate from the metal bonding pad to a back side of the substrate where the via forms a side wall of a via hole. A plurality of the substrates are stacked on one another with the outer end of the solder bump of one substrate fitting within the via hole of an adjacent substrate. During reflow soldering, surface tension forces of the molten solder bump self-align the substrates.
摘要翻译：半导体器件，微机电系统封装及其制造方法利用用于垂直IC封装的高性能通孔。器件/封装的半导体管芯具有形成在衬底前侧上的集成电路的衬底。金属焊盘覆盖在衬底的正面上的衬底上，并与集成电路电连接。焊料凸块位于金属焊盘上。导电通孔延伸穿过衬底从金属接合垫延伸到衬底的背面，其中通孔形成通孔的侧壁。多个基板彼此堆叠，一个基板的焊料凸块的外端装配在相邻基板的通孔内。在回流焊接期间，熔融焊料凸块的表面张力自动对准衬底。

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