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1. 发明授权

US5177582A CMOS-compatible bipolar transistor with reduced collector/substrate capacitance and process for producing the same 失效
标题翻译：具有降低的集电极/衬底电容的CMOS兼容双极晶体管及其制造方法
公开(公告)号：US5177582A
公开(公告)日：1993-01-05
申请号：US754377
申请日：1991-08-30
申请人： Thomas Meister , Hans-Willi Meul , Helmut Klose , Hermann Wendt
发明人： Thomas Meister , Hans-Willi Meul , Helmut Klose , Hermann Wendt
IPC分类号： H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/732
CPC分类号： H01L29/0826 , H01L21/8249 , H01L27/0623 , H01L29/732
摘要： A bipolar transistor with a collector, a base and an emitter disposed in vertical succession includes a semiconductor substrate, insulating oxide zones disposed in the substrate for separating adjacent transistors, and a buried collector terminal layer at least partly disposed on the insulating oxide zones. An insulator structure laterally surrounding a collector. A subcollector is surrounded by the insulating oxide zones, has the same conductivity type with a lower impedance than the collector, is disposed under the collector and under the insulator structure, and is electrically connected to the collector. The insulator structure covers the buried collector terminal layer, laterally insulates the collector from the buried collector terminal layer, and has lateral surfaces extending inside the insulating oxide regions up to the subcollector. The buried collector terminal layer is in direct contact with the subcollector. The collector is electrically connected to the buried collector terminal layer only through the subcollector. The insulator structure has a contact hole extending to the buried collector terminal layer laterally of the active transistor zone, and a metallization filling the contact hole. A process for producing the bipolar transistor includes producing an insulator structure on a substrate for determining a location for a collector; and producing the collector by selective epitaxy only inside the insulator structure, for laterally insulating the collector with the insulator structure. An integrated circuit and method include such bipolar transistors and CMOS transistors.
摘要翻译：具有垂直相继布置的集电极，基极和发射极的双极晶体管包括半导体衬底，设置在衬底中用于分离相邻晶体管的绝缘氧化物区域和至少部分地设置在绝缘氧化物区域上的埋地集电极端子层。横向围绕收集器的绝缘体结构。子集电极被绝缘氧化物区围绕，具有与集电体相比具有较低阻抗的相同的导电类型，设置在集电器下方和绝缘体结构下方，并且与集电极电连接。绝缘体结构覆盖埋地集电极端子层，使集电体与埋地集电极端子层横向绝缘，并且具有在绝缘氧化物区域内延伸直到子集电极的侧表面。埋地集电极端子层与子集电极直接接触。集电极仅通过子集电极电连接到埋地集电极端子层。绝缘体结构具有在有源晶体管区域侧向延伸到集电极端子层的接触孔，以及填充接触孔的金属化。制造双极晶体管的方法包括：在基板上制造用于确定集电体位置的绝缘体结构; 并且仅通过绝缘体结构内的选择性外延生产集电体，用于使绝缘体结构的集电体横向绝缘。集成电路和方法包括这样的双极晶体管和CMOS晶体管。

2. 发明授权

US5498567A Method for manufacturing a laterally limited, single-crystal region on a substrate and the employment thereof for the manufacture of an MOS transistor and a bipolar transistor 失效
标题翻译：用于制造衬底上的横向受限的单晶区域的方法及其用于制造MOS晶体管和双极晶体管的方法
公开(公告)号：US5498567A
公开(公告)日：1996-03-12
申请号：US379861
申请日：1995-04-03
申请人： Helmut Klose , Thomas Meister , Hans-Willi Meul , Reinhard Stengl
发明人： Helmut Klose , Thomas Meister , Hans-Willi Meul , Reinhard Stengl
IPC分类号： H01L21/76 , H01L21/20 , H01L21/331 , H01L21/336 , H01L29/73 , H01L29/732 , H01L29/78
CPC分类号： H01L29/66287 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02505 , H01L21/02532 , H01L21/02639 , H01L29/66651 , Y10S148/011
摘要： A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor, including the steps of: a) providing a substrate made of a single crystal semiconductor material; b) forming a first layer on a surface of the substrate, said first layer being selectively etchable with respect to the substrate; c) forming a second layer on the first layer, the second layer being selectively etchable with respect to the first layer; d) providing an opening in the first and second layers so as to expose an area on the surface of the substrate; e) selectively etching the first layer with respect to the substrate and the second layer so as to provide an undercut between the second layer and the surface of the substrate; f) forming a single crystal region on the exposed surface of the substrate by selective epitaxy: g) doping the second layer such that parts of the second layer adjoining the single-crystal region acting as a channel region form a source region and a drain region; h) producing a gate dielectric at a surface of the single-crystal region; and i) forming a gate electrode that is insulated from the source and drain regions on the gate dielectric.
摘要翻译：一种用于制造适合用作晶体管的有源部分的横向受限单晶区域的方法，包括以下步骤：a）提供由单晶半导体材料制成的衬底; b）在所述衬底的表面上形成第一层，所述第一层相对于所述衬底可选择性地蚀刻; c）在所述第一层上形成第二层，所述第二层可相对于所述第一层选择性地蚀刻; d）在所述第一层和所述第二层中设置开口以暴露所述基底表面上的区域; e）相对于所述基底和所述第二层选择性地蚀刻所述第一层，以便在所述第二层和所述基底的表面之间提供底切; f）通过选择性外延在衬底的暴露表面上形成单晶区域：g）掺杂第二层，使得与用作沟道区的单晶区相邻的第二层的部分形成源区和漏区 ; h）在单晶区域的表面产生栅电介质; 以及i）形成与栅极电介质上的源极和漏极区域绝缘的栅电极。

3. 发明授权

US5422303A Method for manufacturing a laterally limited, single-crystal region on a substrate and the employment thereof for the manufacture of an MOS transistor and a bipolar transistor 失效
标题翻译：用于制造衬底上的横向受限的单晶区域的方法及其用于制造MOS晶体管和双极晶体管的方法
公开(公告)号：US5422303A
公开(公告)日：1995-06-06
申请号：US185514
申请日：1994-01-24
申请人： Helmut Klose , Thomas Meister , Hans-Willi Meul , Reinhard Stengl
发明人： Helmut Klose , Thomas Meister , Hans-Willi Meul , Reinhard Stengl
IPC分类号： H01L21/76 , H01L21/20 , H01L21/331 , H01L21/336 , H01L29/73 , H01L29/732 , H01L29/78
CPC分类号： H01L29/66287 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02505 , H01L21/02532 , H01L21/02639 , H01L29/66651 , Y10S148/011
摘要： A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor, including the steps of: a) providing a substrate made of a single crystal semiconductor material; b) forming a first layer on a surface of the substrate, said first layer being selectively etchable with respect to the substrate; c) forming a second layer on the first layer, the second layer being selectively etchable with respect to the first layer; d) providing an opening in the first and second layers so as to expose an area on the surface of the substrate; e) covering surfaces and sidewalls of the second layer with a third layer f) selectively etching the first layer with respect to the substrate and the second layer and the third layer so as to provide an undercut between the second layer and the surface of the substrate; g) forming a single crystal region on the exposed surface of the substrate by selective epitaxy without nucleation occurring at the surface of the third layer; h) forming a collector in the substrate under the single-crystal region; i) forming a base in the single-crystal region; j) doping and configuring the second layer such that it forms a base terminal; and k) forming an emitter above the base.
摘要翻译：一种用于制造适合用作晶体管的有源部分的横向受限单晶区域的方法，包括以下步骤：a）提供由单晶半导体材料制成的衬底; b）在所述衬底的表面上形成第一层，所述第一层相对于所述衬底可选择性地蚀刻; c）在所述第一层上形成第二层，所述第二层可相对于所述第一层选择性地蚀刻; d）在所述第一层和所述第二层中设置开口以暴露所述基底表面上的区域; e）用第三层覆盖第二层的表面和侧壁f）相对于衬底和第二层和第三层选择性地蚀刻第一层，以便在第二层和衬底的表面之间提供底切 ; g）通过选择性外延在第三层的表面上没有成核而在衬底的暴露表面上形成单晶区; h）在单晶区域下在衬底中形成集电体; i）在单晶区域形成碱; j）掺杂和配置第二层，使得它形成基极; 和k）在基底上形成发射体。

4. 发明授权

US5326718A Method for manufacturing a laterally limited, single-crystal region on a substrate and the employment thereof for the manufacture of an MOS transistor and a bipolar transistor 失效
标题翻译：用于制造衬底上的横向受限的单晶区域的方法及其用于制造MOS晶体管和双极晶体管的方法
公开(公告)号：US5326718A
公开(公告)日：1994-07-05
申请号：US950068
申请日：1992-09-23
申请人： Helmut Klose , Thomas Meister , Hans-Willi Meul , Reinhard Stengl
发明人： Helmut Klose , Thomas Meister , Hans-Willi Meul , Reinhard Stengl
IPC分类号： H01L21/76 , H01L21/20 , H01L21/331 , H01L21/336 , H01L29/73 , H01L29/732 , H01L29/78
CPC分类号： H01L29/66287 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02505 , H01L21/02532 , H01L21/02639 , H01L29/66651 , Y10S148/011
摘要： A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor.
摘要翻译：一种用于制造适合用作晶体管的有源部分的横向受限的单晶区域的方法。

5. 发明授权

US5402002A Bipolar transistor with reduced base/collector capacitance 失效
标题翻译：具有降低的基极/集电极电容的双极晶体管
公开(公告)号：US5402002A
公开(公告)日：1995-03-28
申请号：US737607
申请日：1991-07-24
申请人： Thomas Meister , Hans-Willi Meul
发明人： Thomas Meister , Hans-Willi Meul
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L29/08 , H01L29/732 , H01L29/72
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/0821 , H01L29/732
摘要： A bipolar transistor includes insulator structures defining an active transistor zone having a base, an emitter with a side facing away from the base, and a collector with a collector terminal having a side facing away from the base. The insulator structures are disposed on the sides of the emitter and the collector terminal facing away from the base, and the insulator structures limit current flow through the active transistor zone. A process for producing the bipolar transistor includes producing a collector by selective epitaxy on a zone of a substrate surrounded by insulators. A zone for the collector is defined with a spacer technique in the following steps: photolithographically producing a first opening in a first layer exposing a surface of a second layer; including at least one insulation layer in the second layer; producing spacers at edges of the first opening; and etching a second opening in the second layer defining the zone for the collector during selective back-etching of the spacers.
摘要翻译：双极晶体管包括限定具有基极的有源晶体管区域的绝缘体结构，具有背离基极的一侧的发射极和具有背离基极的一侧的集电极端子的集电极。绝缘体结构设置在发射极和集电极端子背离基极的侧面上，绝缘体结构限制电流通过有源晶体管区域流动。制造双极晶体管的工艺包括通过在由绝缘体包围的衬底的区域上进行选择性外延生产集电极。采用隔离技术在以下步骤中限定用于收集器的区域：光刻地产生暴露第二层表面的第一层中的第一开口; 包括在所述第二层中的至少一个绝缘层; 在所述第一开口的边缘处产生间隔物; 以及在所述间隔物的选择性反向蚀刻期间蚀刻限定所述收集器区域的所述第二层中的第二开口。

6. 发明授权

US5188977A Method for manufacturing an electrically conductive tip composed of a doped semiconductor material 失效
标题翻译：用于制造掺杂半导体材料的电导体尖端的方法
公开(公告)号：US5188977A
公开(公告)日：1993-02-23
申请号：US802811
申请日：1991-12-06
申请人： Reinhard Stengl , Hans-Willi Meul , Wolfgang Hoenlein
发明人： Reinhard Stengl , Hans-Willi Meul , Wolfgang Hoenlein
IPC分类号： H01J1/30 , H01J1/304 , H01J9/02 , H01L21/20 , H01L21/306 , H01L45/00
CPC分类号： H01J9/025 , H01J1/3042 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01J2201/30426 , Y10S148/05
摘要： For manufacturing an electrically conductive tip composed of a doped semiconductor material, a mask layer is produced on a substrate composed of the semiconductor material. This mask layer contains a material at least at its surface and directly on the substrate whereon the semiconductor material does not grow in a selective epitaxy. An opening wherein the surface of the substrate lies exposed is produced in the mask layer. The electrically conductive tip is produced by a selective epitaxy on the exposed surface of the substrate such that the layer growth in the direction parallel to the surface of the substrate is lower than in the direction perpendicular to the surface of the substrate.
摘要翻译：为了制造由掺杂半导体材料构成的导电尖端，在由半导体材料构成的基板上制造掩模层。该掩模层至少在其表面包含材料，并且直接在衬底上，半导体材料不会在选择性外延生长中。在掩模层中产生其中裸露表面露出的开口。通过在衬底的暴露表面上的选择性外延产生导电尖端，使得沿与衬底表面平行的方向上的层生长低于垂直于衬底表面的方向。

7. 发明授权

US4829015A Method for manufacturing a fully self-adjusted bipolar transistor 失效
标题翻译：制造完全自调节双极晶体管的方法
公开(公告)号：US4829015A
公开(公告)日：1989-05-09
申请号：US170897
申请日：1988-03-21
申请人： Hans-Christian Schaber , Hans-Willi Meul
发明人： Hans-Christian Schaber , Hans-Willi Meul
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L29/732
CPC分类号： H01L21/8222 , H01L29/7325 , Y10S148/01 , Y10S148/011 , Y10S148/017
摘要： A method for manufacturing a fully self-adjustsed bipolar transistor in which the emitter zone, the base zone, and the collector zone are aligned vertically in a silicon substrate; the collector is connected by means of a deeply extending terminal in the substrate, the inactive base zone is embedded in an insulating trench to separate the inactive base zone from the collector; the emitter terminal zone is composed of doped polycrystalline silicon and is separated from the inactive base zone by a silicon oxide layer. A fully self-adjusted bipolar transistor is produced wherein the emitter is self-adjusted relative to the base and the base is self-adjusted relative to the insulation. The number of method steps involving critical mask usage is low, and parasitic regions are minimized so that the switching speed of the component is increased. The transistor is used for integrated bipolar transistor circuits having high switching speeds.
摘要翻译：一种制造完全自调节的双极晶体管的方法，其中发射极区，基极区和集电区在硅衬底中垂直排列; 集电极通过在衬底中的深度延伸的端子连接，非活性基区被嵌入在绝缘沟槽中以将非活性基区与收集器分离; 发射极端子区由掺杂的多晶硅组成，并通过氧化硅层与非活性基极区分离。制造完全自调节的双极晶体管，其中发射极相对于基底自我调节，并且基底相对于绝缘体自我调节。涉及关键掩模使用的方法步骤的数量很少，寄生区域被最小化，使得部件的切换速度增加。晶体管用于具有高开关速度的集成双极晶体管电路。

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