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1. 发明申请

US20120220133A1 Integrated Circuit Having Interleaved Gridded Features, Mask Set, and Method for Printing 有权
标题翻译：具有交错网格特征的集成电路，掩模套和打印方法
公开(公告)号：US20120220133A1
公开(公告)日：2012-08-30
申请号：US13447629
申请日：2012-04-16
申请人： Thomas J. Aton , Donald Plumton
发明人： Thomas J. Aton , Donald Plumton
IPC分类号： H01L21/32
CPC分类号： H01L21/31144 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer.
摘要翻译：一种用于制造集成电路的方法包括以下步骤：提供具有半导体表面的衬底; 在半导体表面上提供硬掩模材料。对于集成电路的至少一个掩蔽级别：提供分割为第一掩模和至少一个第二掩模的掩蔽级别的掩模图案，所述第一掩模提供第一栅格图案中的特征，并且所述至少一个第二掩模提供特征在第二格栅图案中，其中第一和第二格栅图案具有在至少一个区域上彼此交错的各自特征; 用第一掩模施加第一光致抗蚀剂层; 使用第一掩模曝光第一格栅图案; 显影第一光致抗蚀剂层; 蚀刻硬掩模材料以将衬底的表面中的第一栅格图案转移; 去除第一光致抗蚀剂层。

2. 发明申请

US20120074973A1 ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS 有权
标题翻译：用于在线监测上下文相关效果的模拟参数测试模块
公开(公告)号：US20120074973A1
公开(公告)日：2012-03-29
申请号：US12890146
申请日：2010-09-24
申请人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
发明人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
IPC分类号： G01R31/3187
CPC分类号： G01R31/2831
摘要： An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.
摘要翻译：集成电路（IC）管芯具有管芯上的参数测试模块。半导体衬底具有管芯区域，以及形成在管芯区域的IC部分上的功能IC，包括被配置为执行电路功能的多个电路元件。在与IC部分不同的管芯区域的一部分中，在半导体衬底上形成管芯上参数测试模块。片上参数测试模块包括提供至少一个有源参考MOS晶体管的参考布局，其中有源参考MOS晶体管具有针对多个上下文相关效应参数中的每一个的参考间隔值。在片上参数测试模块上包括多个不同的变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

3. 发明申请

US20090125865A1 SYSTEM AND METHOD FOR MAKING PHOTOMASKS 有权
标题翻译：制作光子的系统和方法
公开(公告)号：US20090125865A1
公开(公告)日：2009-05-14
申请号：US11940270
申请日：2007-11-14
申请人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
发明人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
IPC分类号： G06F17/50 , H05K1/00
CPC分类号： G03F1/36
摘要： The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.
摘要翻译：本公开涉及一种制备光掩模图案的方法。该方法包括接收用于设计数据库的绘制图案数据。所绘制的图案数据描述了第一设备特征和第二设备特征，第二设备特征与用于向第二设备特征提供第一设备特征的期望连接性的设计规范相关联。至少第一多个第一设备特征具有不会导致足够的覆盖以实现期望的连接性的图形。为第一器件特征形成光掩模图案，其中用于第一多个第一器件特征的光掩模图案将导致期望的覆盖。还教导了使用本公开的原理形成的集成电路器件。

4. 发明申请

US20070287507A1 System and method for automatically toggling the alert of a wireless device 审中-公开
标题翻译：自动切换无线设备的警报的系统和方法
公开(公告)号：US20070287507A1
公开(公告)日：2007-12-13
申请号：US11450447
申请日：2006-06-12
申请人： Thomas J. Aton , Beatrice Rapley Aton
发明人： Thomas J. Aton , Beatrice Rapley Aton
IPC分类号： H04B1/38 , G08B5/22 , G08B7/00
CPC分类号： H04M19/04 , H04W4/021 , H04W4/16
摘要： A system and method for communicating with a wireless device to automatically toggle the alert. The control station automatically transmits at least one signal to the wireless device, which instructs the wireless device to use a silent alert. The control station can also include a database for storing identifiers of wireless devices having users who must remain available, allowing those wireless devices to use a tactile alert instead of a silent alert. The control station can automatically instruct the wireless device to use a silent alert, a tactile alert, or an audible alert depending upon the time of day.
摘要翻译：用于与无线设备通信以自动切换警报的系统和方法。控制站自动向无线设备发送至少一个信号，无线设备指示无线设备使用无声警报。控制站还可以包括用于存储具有必须保持可用的用户的无线设备的标识符的数据库，允许这些无线设备使用触觉警报而不是静默警报。控制站可以根据一天中的时间自动地指示无线设备使用无声警报，触觉警报或可听警报。

5. 发明授权

US06553558B2 Integrated circuit layout and verification method 有权
公开(公告)号：US06553558B2
公开(公告)日：2003-04-22
申请号：US09737680
申请日：2000-12-14
申请人： Shane R. Palmer , John N. Randall , Thomas J. Aton
发明人： Shane R. Palmer , John N. Randall , Thomas J. Aton
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F7/70441
摘要： A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction techniques are then applied to the mask layout data. Theoretical contours which comprise curvilinear forms are then extrapolated from the corrected mask data set. The curvilinear contour data is then bounded using boxing algorithms in order to generate a bounded contour data set. The bounded contour data set can then be compared to the original input mask data to detect design rule violations and other characteristics of the original layout.

6. 发明授权

US06486525B1 Deep trench isolation for reducing soft errors in integrated circuits 有权
公开(公告)号：US06486525B1
公开(公告)日：2002-11-26
申请号：US09353478
申请日：1999-07-13
申请人： Thomas J. Aton
发明人： Thomas J. Aton
IPC分类号： H01L2900
CPC分类号： H01L21/823481 , H01L21/76224
摘要： An integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit are disclosed. The integrated circuit comprises a substrate 72, a transistor formed in the substrate 72, a first region 74 (e.g. a well) formed in the substrate having a first conductivity type, a second region 84 below the first region 74 having a second conductivity type, and a trench formed in the substrate having a depth at least substantially as deep as the well. The trench 70 is filled with a non-conductive material 71 that forms a frame around the transistor, whereby soft errors due to electron-hole pairs caused by ionizing radiation in the frame are substantially eliminated.

7. 发明授权

US5929645A Integrated circuit tester using ion beam 失效
标题翻译：集成电路测试仪采用离子束
公开(公告)号：US5929645A
公开(公告)日：1999-07-27
申请号：US846062
申请日：1997-04-25
申请人： Thomas J. Aton
发明人： Thomas J. Aton
IPC分类号： G01R31/303 , G01R31/26 , G01R31/305
CPC分类号： G01R31/303 , G01R31/31816
摘要： Testing an Integrated circuit (420) for performance during exposure to an ion beam. Ion beams of atoms with atomic weights in the range of 6 to 20 impinging on an integrated circuit simulate the effects of cosmic ray neutrons interacting with silicon atoms of the integrated circuit.
摘要翻译：测试集成电路（420），用于在暴露于离子束期间执行性能。原子量在6到20范围内的原子量的离子束撞击在集成电路上，模拟与集成电路的硅原子相互作用的宇宙射线中子的影响。

8. 发明授权

US5406116A Dopant implant for conductive charge leakage layer for use with voltage contrast 失效
标题翻译：用于电压对比的导电电荷泄漏层的掺杂剂注入
公开(公告)号：US5406116A
公开(公告)日：1995-04-11
申请号：US162813
申请日：1993-12-06
申请人： Kendall S. Wills , John S. Bartlett , Thomas J. Aton , David E. Littlefield
发明人： Kendall S. Wills , John S. Bartlett , Thomas J. Aton , David E. Littlefield
IPC分类号： G01R31/307 , H01L23/31 , H01L29/34 , H01L21/22
CPC分类号： H01L23/3171 , G01R31/307 , H01L2924/0002 , Y10S438/958
摘要： A layer of dopant is implanted in the passivation of a semiconductor die to facilitate testing of the die by a scanning electron microscope voltage contrast system. The layer of dopant is capacitively coupled to circuits under the passivation and is coupled to ground to allow charge to bleed to ground through a high resistivity path. The resistivity is low enough to allow E-beam charge bleed off, but not bleed off of higher frequency capacitive coupled signals. The disclosure is also applicable to photo generated electron voltage contrast.
摘要翻译：在半导体管芯的钝化中注入掺杂剂层，以便通过扫描电子显微镜电压对比度系统来测试管芯。掺杂剂层电容耦合到钝化下的电路，并且耦合到地，以允许电荷通过高电阻率路径渗出到地。电阻率足够低以允许电子束电荷泄漏，但不会泄漏更高频率的电容耦合信号。本公开也适用于光电生成电子电压对比度。

9. 发明授权

US5367702A System and method for approximating nonlinear functions 失效
标题翻译：用于近似非线性函数的系统和方法
公开(公告)号：US5367702A
公开(公告)日：1994-11-22
申请号：US000071
申请日：1993-01-04
申请人： Shivaling S. Mahant-Shetti , Thomas J. Aton , Jerold A. Seitchik
发明人： Shivaling S. Mahant-Shetti , Thomas J. Aton , Jerold A. Seitchik
IPC分类号： G06F17/17 , G06F7/552 , G06F15/353
CPC分类号： G06F7/552 , G06F2207/5525
摘要： A system (10) is provided for approximating a nonlinear function. The system (10) comprises first and second multiple generating circuits (12) and (14) for multiplying a first quantity and a second quantity by up to three integer powers of two. First and second function generating circuits (16) and (18) generate first and second functions of the first and the second quantities by combining the multiples generated in first and second multiple generating circuits (12) and (14). First and second approximation generating circuits (20) and (22) generate first and second approximations of the nonlinear function by shifting the output of first and second function generating circuits (16) and (18). Approximation selecting circuit (24) outputs the appropriate approximation generated in first and second approximation generating circuits (20) and (22).
摘要翻译：提供一种用于近似非线性函数的系统（10）。系统（10）包括用于将第一数量和第二数量乘以最多三个整数二的幂数的第一和第二多个产生电路（12）和（14）。第一和第二功能发生电路（16）和（18）通过组合在第一和第二多个发电电路（12）和（14）中产生的倍数来产生第一和第二量的第一和第二功能。第一和第二近似产生电路（20）和（22）通过移位第一和第二函数发生电路（16）和（18）的输出来产生非线性函数的第一和第二近似。近似选择电路（24）输出在第一和第二近似发生电路（20）和（22）中产生的适当近似。

10. 发明授权

US4978908A Scanning electron microscope based parametric testing method and apparatus 失效
公开(公告)号：US4978908A
公开(公告)日：1990-12-18
申请号：US327080
申请日：1989-03-22
申请人： Shivaling S. Mahant-Shetti , Thomas J. Aton , Rebeca J. Gale
发明人： Shivaling S. Mahant-Shetti , Thomas J. Aton , Rebeca J. Gale
IPC分类号： H01J37/28 , G01Q30/02 , G01R31/302 , G01R31/305 , H01L21/66
CPC分类号： G01R31/305
摘要： A scanning electron microscope (28) is connected to a test structure (48) formed on a semiconductor wafer. The test structure (48) comprises a plurality of first parallel structures (54) and a plurality of second parallel structure (56) transverse to and interlocking with the first structures (54). An island (60) is formed within a grid (58) formed by the structures (54-56) and is separated therefrom. An electron beam (38) from the scanning electron microscope (28) is aimed at the structure (48) and secondary electrons emitted therefrom are visually displayed on a monitor (44). The visual display (47) provides information on whether the island (60) is electrically separated from the mesh (58) or shorted thereto by comparing the intensity of the various islands (60).

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