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1. 发明授权

US5438621A DC-free line code and bit and frame synchronization for arbitrary data transmission 失效
标题翻译：无需线路代码以及用于任意数据传输的位和帧同步
公开(公告)号：US5438621A
公开(公告)日：1995-08-01
申请号：US857924
申请日：1992-05-05
申请人： Thomas Hornak , Patrick Petruno , Richard C. Walker , Benny W. H. Lai , Chu-Sun Yen , Cheryl L. Stout , Jieh-Tsorng Wu
发明人： Thomas Hornak , Patrick Petruno , Richard C. Walker , Benny W. H. Lai , Chu-Sun Yen , Cheryl L. Stout , Jieh-Tsorng Wu
IPC分类号： H03M5/14 , H04J3/06 , H04J3/12 , H04L7/04 , H04L25/49
CPC分类号： H04J3/12 , H03M5/145 , H04J3/0602 , H04L25/4915 , H04L2007/045
摘要： A method of encoding data for transmission over a communication link. A cumulative polarity of previously-transmitted frames is maintained. A frame is prepared for transmission by combining a data word with a plurality of additional bits. The additional bits provide a master transition. A phantom bit is encoded in the additional bits. If the polarity of the frame is the same as the cumulative polarity, the data bits or in some instances all the bits are inverted so as to maintain balance. Control words and fill words are provided and are distinguished from data words by encoding the additional bits. Control words carry additional data or control instructions and are distinguished from fill words by the number of transitions. The phantom bit either conveys additional data or is used for such purposes as error checking.
摘要翻译： PCT No.PCT / US91 / 08483 Sec。 371日期：1992年5月5日 102（e）日期1992年5月5日PCT 1991年11月13日PCT PCT。出版物WO92 / 09162 日期：1992年5月29日。一种对通过通信链路传输的数据进行编码的方法。维持先前传输的帧的累积极性。通过组合数据字与多个附加位来准备用于发送的帧。附加位提供主转换。幻像位被编码在附加位中。如果帧的极性与累积极性相同，则数据位或在某些情况下所有位都被反转，以保持平衡。提供控制字和填充字，并通过编码附加位与数据字区分开。控制字携带附加数据或控制指令，并且通过转换次数与填充字区分开。幻影位传送附加数据或用于错误检查等目的。

2. 发明授权

US5012494A Method and apparatus for clock recovery and data retiming for random NRZ data 失效
标题翻译：用于随机NRZ数据的时钟恢复和数据重新定时的方法和装置
公开(公告)号：US5012494A
公开(公告)日：1991-04-30
申请号：US432869
申请日：1989-11-07
申请人： Benny W. H. Lai , Richard C. Walker
发明人： Benny W. H. Lai , Richard C. Walker
IPC分类号： H03K3/03 , H03L7/093 , H03L7/099 , H04L7/033
CPC分类号： H03L7/0995 , H03K3/0315 , H03L7/093 , H04L7/033
摘要： A method and apparatus for recovering a clock signal from a random NRZ data signal is shown to include a phase detector for detecting the phase difference between the random NRZ data signal and a clock signal and for generating a phase signal representative of the phase difference. The phase signal is a binary signal having first and second logic levels, wherein the first logic level is representative of the clock signal having an early phase relationship with the data signal and wherein the second logic level is representative of the clock signal having a late phase relationship with the data signal. Clock recovery also incorporates an integrator for integrating the phase signal over a period of time and for generating an integration signal representative of such integration and an oscillator for generating the clock signal at a clock frequency responsive to both the phase signal and the integration signal. The clock frequency is determined by a centering factor and an offset factor. The centering factor is controlled by the phase signal. There is also shown a particular phase detector, several integrators and a preferred oscillator for practicing the invention.

3. 发明授权

US5498992A Unity gain positive feedback integrator with programmable charging currents and polarities 失效
标题翻译：具有可编程充电电流和极性的Unity增益正反馈积分器
公开(公告)号：US5498992A
公开(公告)日：1996-03-12
申请号：US358031
申请日：1994-12-14
申请人： Benny W. H. Lai , Richard C. Walker
发明人： Benny W. H. Lai , Richard C. Walker
IPC分类号： G06G7/184 , H03K4/58 , H03K4/52 , H03K4/56
CPC分类号： G06G7/184
摘要： An integrator includes a capacitor and a bootstrap circuit for detecting any leaking charge from the capacitor and replacing it. The integrator also includes a charge injection circuit for adjusting the charge applied to the capacitor in response to a digital control input to the charge injection circuit. The bootstrap circuit has two transistors to sense leaking charge, and two further transistors forming a differential pair. The bootstrap circuit uses positive feedback and unity gain to replenish the lost charge.
摘要翻译：积分器包括电容器和自举电路，用于检测来自电容器的任何泄漏电荷并将其替换。积分器还包括一个充电注入电路，用于响应于对电荷注入电路的数字控制输入来调节施加到电容器的电荷。自举电路具有两个用于检测泄漏电荷的晶体管，以及形成差分对的两个另外的晶体管。自举电路使用正反馈和统一增益来补充丢失的电荷。

4. 发明授权

US07079575B2 Equalization for crosspoint switches 失效
公开(公告)号：US07079575B2
公开(公告)日：2006-07-18
申请号：US10066019
申请日：2002-01-30
申请人： Peter Ho , Benny W. H. Lai
发明人： Peter Ho , Benny W. H. Lai
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H03K3/0322 , H03K2005/00026 , H03K2005/00097 , H03L7/085 , H03L7/0998 , H03L2207/06
摘要： Equalization for ports of a crosspoint switch at least partially offsets transmission losses such as skin loss. The equalization may be tailored on a port-by-port basis using adaptive equalization or adjustable equalization, but fixed equalization may be used. In some implementations, each input port or output port of a crosspoint switch has a dedicated equalization circuit that has filtering characteristics that are based on the signal characteristics (e.g., jitter) measured at the affected output port. For an adjustable equalization approach, the adjustable equalization circuitry includes various switched connections that are selectively coupled and decoupled to achieve the target level of equalization.

5. 发明授权

US5473639A Clock recovery apparatus with means for sensing an out of lock condition 失效
标题翻译：具有用于感测出锁定状态的装置的时钟恢复装置
公开(公告)号：US5473639A
公开(公告)日：1995-12-05
申请号：US97688
申请日：1993-07-26
申请人： Donald M. Lee , Benny W. H. Lai
发明人： Donald M. Lee , Benny W. H. Lai
IPC分类号： H03L7/095 , H03L7/099 , H03L7/12 , H04L7/00 , H04L7/033
CPC分类号： H04L7/0083 , H03L7/0995 , H03L7/12 , H04L7/033 , H03L2207/06 , H03L2207/14
摘要： An out of lock condition is sensed on a data transition by transition basis in clock recovery apparatus. When an out of lock condition is sensed, a range sweeping signal is generated and summed with the correction signal to sweep the frequency of the clock signal over the frequency range of the VCO. When an out of lock condition is absent, i.e., when the VCO is phase locked, simulated data transitions are generated in the frequency/phase detector. An out of lock condition is sensed by a D flip-flop. Data is coupled to the clock input of the flip-flop, the clock signal is delayed by a fraction of its nominal period and coupled to the D input of the flip-flop. The state of the Q output of the flip-flop indicates an out of lock condition.
摘要翻译：在时钟恢复装置中通过转换的数据转换来检测出失锁状态。当检测到失锁状态时，产生范围扫描信号并与校正信号相加，以在VCO的频率范围上扫描时钟信号的频率。当不存在锁定状态时，即当VCO被锁相时，在频率/相位检测器中产生模拟数据转换。锁定状态由D触发器感测到。数据耦合到触发器的时钟输入端，时钟信号延迟其标称周期的一小部分并耦合到触发器的D输入端。触发器的Q输出的状态表示失锁状态。

6. 发明授权

US07343535B2 Embedded testing capability for integrated serializer/deserializers 失效
标题翻译：集成串行器/解串器的嵌入式测试功能
公开(公告)号：US07343535B2
公开(公告)日：2008-03-11
申请号：US10068326
申请日：2002-02-06
申请人： Benny W. H. Lai
发明人： Benny W. H. Lai
IPC分类号： G01R31/28 , H04B3/46
CPC分类号： G11C29/56 , G01R31/317 , G01R31/31715 , G01R31/31723 , G01R31/31724 , G01R31/31813 , G11C29/48
摘要： Testing capability for an integrated circuit having more than one serializer/deserializer (SERDES) block includes embedding a tester within each block, so that the blocks can be tested independently and concurrently. In one embodiment, a tester includes a functional test controller (FTC) for mode setting and a functional test interface (FTI) for implementing the test procedures. The FTI of each tester is inserted between the SERDES of the same block and core processing logic that is also embedded within the integrated circuit. The FTCs are all interconnected via a test bus that is connected to an input/output controller (IOC) for communication between the testers and an external source, such as a personal computer. Optionally, a built-in-self-tester (BIST) state machine is connected to the test bus.
摘要翻译：具有多个串行器/解串器（SERDES）块的集成电路的测试功能包括在每个块内嵌入一个测试仪，以便可以独立且同时测试这些模块。在一个实施例中，测试器包括用于模式设置的功能测试控制器（FTC）和用于实现测试过程的功能测试接口（FTI）。每个测试仪的FTI插入同一块的SERDES和嵌入在集成电路中的核心处理逻辑之间。 FTC都通过连接到输入/输出控制器（IOC）的测试总线相互连接，用于测试仪和外部源（如个人计算机）之间的通信。可选地，内置自测试器（BIST）状态机连接到测试总线。

7. 发明授权

US06836852B2 Method for synchronizing multiple serial data streams using a plurality of clock signals 有权
标题翻译：使用多个时钟信号同步多个串行数据流的方法
公开(公告)号：US06836852B2
公开(公告)日：2004-12-28
申请号：US10021133
申请日：2001-10-29
申请人： Charles L. Wang , Benny W. H. Lai , Charles E. Moore , Philip W. Fisher
发明人： Charles L. Wang , Benny W. H. Lai , Charles E. Moore , Philip W. Fisher
IPC分类号： G06F104
CPC分类号： H03L7/06 , H03L7/07
摘要： Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.
摘要翻译：本文公开了用于生成和同步多个时钟的方法和系统，其在多个信道上具有极低的偏移，并且最小和明确定义的等待时间。锁相环电路产生多个时钟信号以同步接收核心数据流的信道电路。通道电路将核心数据流转换为串行数据流。锁相环电路或另一个锁相环电路产生核心时钟信号，用于核心数据流的注册传输到信道电路。多个时钟信号中的一个或多个可以通过寄存器到寄存器传送分配给信道电路。

8. 发明授权

US06700942B1 Parallel automatic synchronization system (PASS) 失效
标题翻译：并行自动同步系统（PASS）
公开(公告)号：US06700942B1
公开(公告)日：2004-03-02
申请号：US09343312
申请日：1999-06-30
申请人： Benny W. H. Lai
发明人： Benny W. H. Lai
IPC分类号： H04L700
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/0041
摘要： A parallel automatic synchronization system includes a variable delay devices for receiving and variably delaying N parallel transmitted channel data words over repetitive clock cycles in response to a synchronization latch clock and for synchronously clocking out the parallel data words by a local reference clock (FREF); sync logic devices for receiving repetitive control clocks corresponding to the transmitted channel data words, including a remote recovered clock (FFRM) and the local reference clock (FREF) and for generating the synchronization latch clock which determines the delay position of the variable delay of the delay devices; and output latch devices for clocking out the parallel data words from the variable delay devices with the local reference clock (FREF).
摘要翻译：并行自动同步系统包括可变延迟装置，用于响应于同步锁存时钟在重复时钟周期上接收和可变地延迟N个并行发送的信道数据字，并用于通过本地参考时钟（FREF）同步计时并行数据字; 同步逻辑设备，用于接收对应于所发送的信道数据字的重复控制时钟，包括远程恢复时钟（FFRM）和本地参考时钟（FREF），并用于产生同步锁存时钟，其确定可变延迟的延迟位置延迟装置; 并输出锁存器件，用于使用本地参考时钟（FREF）从可变延迟器件中计时并行数据字。

9. 发明授权

US06526112B1 System for clock and data recovery for multi-channel parallel data streams 失效
标题翻译：用于多通道并行数据流的时钟和数据恢复系统
公开(公告)号：US06526112B1
公开(公告)日：2003-02-25
申请号：US09342297
申请日：1999-06-29
申请人： Benny W. H. Lai
发明人： Benny W. H. Lai
IPC分类号： H03D2300
CPC分类号： H03L7/0805 , H03L7/07 , H03L2207/06 , H04L7/033 , H04L25/14
摘要： The present invention provides independent CDR (clock and data recovery) functions on N number of high speed parallel channels, yet only requiring one capacitor. This enables multiple independent CDR channels to be integrated onto one IC with a minimum overhead component of one capacitor. In one embodiment, the present invention provides a multiple channel clock and data recovery system which includes N phase lock loop circuits for receiving in parallel N data channels, each of the N phase lock loop circuits including a digital phase detector and a dual-input VCO in which one VCO input is an analog input for setting the center frequency of the VCO and the other VCO input is a digital input from the respective phase detector for toggling the center frequency and wherein each phase detector compares the phase of the respective incoming data channel with that of the respective VCO output. The system further includes a first phase lock loop circuit of the N phase lock loop circuits further including an integrator having a single capacitor, the integrator connected between the output of the first phase detector and the analog input of the respective first VCO wherein the output of the first phase detector is input to the integrator, the output of the integrator is also input to the remaining analog inputs of the other VCOs such that the remaining phase lock loop circuits are slaved to the first phase lock loop circuit.
摘要翻译：本发明在N个高速并行信道上提供独立的CDR（时钟和数据恢复）功能，但仅需要一个电容器。这使得多个独立CDR信道可以集成到一个IC上，同时具有一个电容器的最小开销成分。在一个实施例中，本发明提供一种多通道时钟和数据恢复系统，其包括用于并行接收N个数据通道的N个锁相环电路，N个锁相环电路中的每一个包括数字相位检测器和双输入VCO 其中一个VCO输入是用于设置VCO的中心频率的模拟输入，另一个VCO输入是来自各个相位检测器的用于切换中心频率的数字输入，并且其中每个相位检测器比较各个输入数据信道的相位与相应的VCO输出。该系统还包括N个锁相环电路的第一锁相环电路，还包括具有单个电容器的积分器，该积分器连接在第一相位检测器的输出端和相应第一VCO的模拟输入端之间，第一相位检测器被输入到积分器，积分器的输出也被输入到其它VCO的剩余模拟输入，使得剩余的锁相环电路从动到第一锁相环电路。

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