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1. 发明申请

US20050283679A1 Method, system, and computer program product for dynamically managing power in microprocessor chips according to present processing demands 有权
标题翻译：方法，系统和计算机程序产品，用于根据当前的处理需求动态管理微处理器芯片的电源
公开(公告)号：US20050283679A1
公开(公告)日：2005-12-22
申请号：US10860407
申请日：2004-06-03
申请人： Thomas Heller , Michael Ignatowski , Bernard Meyerson , James Rymarczyk
发明人： Thomas Heller , Michael Ignatowski , Bernard Meyerson , James Rymarczyk
IPC分类号： G06F1/32 , G06F11/00
CPC分类号： G06F1/32 , G06F1/3203 , G06F1/3287 , G06F9/30101 , G06F9/3885 , Y02D10/171 , Y02D50/20
摘要： A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于在包括微处理器芯片内的物理硬件元件的微处理器芯片中动态管理电力。选择执行一个进程。然后识别执行该过程所需的硬件元素。微处理器芯片中的电源通过改变被识别为必要的硬件元件的当前功率状态来动态地改变。

2. 发明授权

US09135185B2 Die-stacked memory device providing data translation 有权
标题翻译：提供数据转换的堆叠式存储器件
公开(公告)号：US09135185B2
公开(公告)日：2015-09-15
申请号：US13726143
申请日：2012-12-23
申请人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
发明人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/1027 , H01L25/18 , H01L2224/16225 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.
摘要翻译：芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。

3. 发明授权

US08879301B2 Method and apparatus for controlling state information retention in an apparatus 有权
标题翻译：用于控制装置中的状态信息保持的方法和装置
公开(公告)号：US08879301B2
公开(公告)日：2014-11-04
申请号：US13616142
申请日：2012-09-14
申请人： David Mayhew , Mark Hummel , Michael Ignatowski
发明人： David Mayhew , Mark Hummel , Michael Ignatowski
IPC分类号： G11C11/00 , G11C13/00 , G11C14/00 , H03K19/00 , G11C11/412 , G11C5/00
CPC分类号： G11C13/0002 , G11C5/005 , G11C11/4125 , G11C14/0045 , H03K19/0016 , H03K19/0019
摘要： A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore condition, the method and apparatus controls either or both of saving or restoring of state information for different virtual machines operating on the processing circuit, into corresponding on-die persistent passive variable resistance memory. The state information save or restore condition is a virtual machine level state information save or restore condition. State information for each of differing virtual machines is saved or restored from differing on-die passive variable resistance memory cells that are assigned on a per-virtual machine basis.
摘要翻译：用于控制状态信息保持的方法和装置至少确定集成电路中至少一个处理电路（例如一个或多个CPU或GPU核心或管线）的状态信息保存或恢复条件。响应于确定状态信息保存或恢复条件，该方法和装置控制将处理电路上运行的不同虚拟机的状态信息的保存或恢复中的任一个或两者转换为相应的裸片上持续的可变电阻存储器。状态信息保存或恢复条件是虚拟机级状态信息保存或恢复条件。每个不同虚拟机的状态信息由在每个虚拟机基础上分配的不同的片上可变电阻存储器单元进行保存或恢复。

4. 发明授权

US08122216B2 Systems and methods for masking latency of memory reorganization work in a compressed memory system 失效
标题翻译：用于屏蔽存储器重组延迟的系统和方法在压缩存储器系统中工作
公开(公告)号：US08122216B2
公开(公告)日：2012-02-21
申请号：US11516207
申请日：2006-09-06
申请人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
发明人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/08 , G06F12/0804 , G06F12/1408 , G06F2212/401
摘要： Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
摘要翻译：提供了计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩盖在访问压缩主存储器之后与存储器重组工作相关联的等待时间。特别地，实现数据块缓冲器和优先级调度协议以延迟和优先化存储器重组工作，以允许资源用于服务新的存储器访问请求和其他高优先级命令。

5. 发明授权

US07099816B2 Method, system and article of manufacture for an analytic modeling technique for handling multiple objectives 有权
公开(公告)号：US07099816B2
公开(公告)日：2006-08-29
申请号：US10174030
申请日：2002-06-17
申请人： Michael Ignatowski , Noshir Cavas Wadia , Peng Ye
发明人： Michael Ignatowski , Noshir Cavas Wadia , Peng Ye
IPC分类号： G06F9/455 , G06F13/00
CPC分类号： G06Q10/04 , G06F11/3419 , G06F11/3447
摘要： The present invention discloses a method, system and article of manufacture for performing analytic modeling on a computer system by handling a plurality of predefined system criteria directed to a modeled computer system. The present invention provides means for the user of an analytic model to specify (i.e. enable) any number of predefined system criteria that must all be simultaneously satisfied. The modeling methodology uses a variation of the well-known Mean Value Analysis technique in its calculations. Response times, resource utilizations, and resource queue lengths are initially estimated for a small user arrival rate. An iterative method is used to gradually increase the user arrival rate by a constant value. For each iteration, response times, resource utilizations, and resource queue lengths are calculated. Then for all the criteria, which have been enabled, it is checked to see if the value limits specified for those criteria have exceeded. If not, the model calculation results are saved and next iteration is started. The model iterations continue with a gradually increasing user arrival rate until one or more of the modeling criteria are exceeded. At that time the model outputs the results from the previous iteration (i.e. the saved results where all the criteria were still satisfied), and the modeling calculations are finished. The model results may be used as input for further processing.

6. 发明申请

US20130159812A1 MEMORY ARCHITECTURE FOR READ-MODIFY-WRITE OPERATIONS 审中-公开
标题翻译：用于读写操作的存储器架构
公开(公告)号：US20130159812A1
公开(公告)日：2013-06-20
申请号：US13328393
申请日：2011-12-16
申请人： Gabriel H. LOH , James M. O'Connor , Michael Ignatowski , Nuwan S. Jayasena , Bradford M. Beckmann
发明人： Gabriel H. LOH , James M. O'Connor , Michael Ignatowski , Nuwan S. Jayasena , Bradford M. Beckmann
IPC分类号： H03M13/09 , G06F11/10 , G06F12/00
CPC分类号： G11C5/02 , G06F11/1048
摘要： According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data.
摘要翻译：根据一个实施例，提供了一种存储器架构实现的方法，其中存储器架构包括逻辑芯片和单个管芯上的一个或多个存储器芯片，并且其中该方法包括：从一个或多个存储器芯片读取数据的值逻辑芯片，其中一个或多个存储器芯片和逻辑芯片在单个芯片上; 通过单个芯片上的逻辑芯片修改数据的值; 并从逻辑芯片向一个或多个存储器芯片写入修改的数据值。

7. 发明授权

US08028290B2 Multiple-core processor supporting multiple instruction set architectures 有权
标题翻译：支持多指令集架构的多核处理器
公开(公告)号：US08028290B2
公开(公告)日：2011-09-27
申请号：US11468547
申请日：2006-08-30
申请人： James Walter Rymarczyk , Michael Ignatowski , Thomas J. Heller, Jr.
发明人： James Walter Rymarczyk , Michael Ignatowski , Thomas J. Heller, Jr.
IPC分类号： G06F9/46 , G06F15/00 , G06F15/76
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.
摘要翻译：在为多个指令集架构（ISA）需要多重支持的虚拟机环境中提供功率高效灵活的平台的系统中支持多指令集架构。处理器包括具有不同的本机ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。虚拟机管理程序控制核心的操作，定位核心，并在必要时启用实例化具有指定ISA的虚拟机的请求。 ISA可以由特定的操作系统和/或应用程序要求来指定。

8. 发明申请

US20080229128A1 System and Computer Program Product for Dynamically Managing Power in MicroProcessor Chips According to Present Processing Demands 有权
标题翻译：根据当前处理要求，微处理器芯片动态管理系统和计算机程序产品
公开(公告)号：US20080229128A1
公开(公告)日：2008-09-18
申请号：US12131507
申请日：2008-06-02
申请人： Thomas J. Heller , Michael Ignatowski , Bernard Steele Meyerson , James Walter Rymarczyk
发明人： Thomas J. Heller , Michael Ignatowski , Bernard Steele Meyerson , James Walter Rymarczyk
IPC分类号： G06F1/00
CPC分类号： G06F1/32 , G06F1/3203 , G06F1/3287 , G06F9/30101 , G06F9/3885 , Y02D10/171 , Y02D50/20
摘要： A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于在包括微处理器芯片内的物理硬件元件的微处理器芯片中动态管理电力。选择执行一个进程。然后识别执行该过程所需的硬件元素。微处理器芯片中的电源通过改变被识别为必要的硬件元件的当前功率状态来动态地改变。

9. 发明申请

US20080059728A1 Systems and methods for masking latency of memory reorganization work in a compressed memory system 失效
标题翻译：用于屏蔽存储器重组延迟的系统和方法在压缩存储器系统中工作
公开(公告)号：US20080059728A1
公开(公告)日：2008-03-06
申请号：US11516207
申请日：2006-09-06
申请人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
发明人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
IPC分类号： G06F13/28
CPC分类号： G06F12/08 , G06F12/0804 , G06F12/1408 , G06F2212/401
摘要： Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
摘要翻译：提供了计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩盖在访问压缩主存储器之后与存储器重组工作相关联的等待时间。特别地，实现数据块缓冲器和优先级调度协议以延迟和优先化存储器重组工作，以允许资源用于服务新的存储器访问请求和其他高优先级命令。

10. 发明授权

US06457100B1 Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls 失效
标题翻译：可扩展的共享存储器多处理器计算机系统具有重复的芯片结构，具有高效的布线和一致性控制
公开(公告)号：US06457100B1
公开(公告)日：2002-09-24
申请号：US09396319
申请日：1999-09-15
申请人： Michael Ignatowski , Thomas James Heller, Jr. , Gottfried Andreas Goldiran
发明人： Michael Ignatowski , Thomas James Heller, Jr. , Gottfried Andreas Goldiran
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/082 , G06F2212/2542
摘要： A novel structure for a highly-scaleable high-performance shared-memory computer system having simplified manufacturability. The computer system contains a repetition of system cells, in which each cell is comprised of a processor chip and a memory subset (having memory chips such as DRAMs or SRAMs) connected to the processor chip by a local memory bus. A unique type of intra-nodal busing connects each system cell in each node to each other cell in the same node. The memory subsets in the different cells need not have equal sizes, and the different nodes need not have the same number of cells. Each node has a nodal cache, a nodal directory and nodal electronic switches to manage all transfers and data coherence among all cells in the same node and in different nodes. The collection of all memory subsets in the computer system comprises the system shared memory, in which data stored in any memory subset is accessible to the processors on the other processor chips in the system. Each location in the system shared memory has a unique real address, which may be used by any processor in the system. Thus, the same memory addresses may be used in the executable instructions of all processors in the system. The nodal directories automatically manage the coherence of all data being changed in all processor caches in the computer system, regardless of where the data is stored in the shared memory of the system and regardless of which cell in the system contains the processor changing the data to provide data coherence across all nodes in the computer system.
摘要翻译：一种高度可扩展的高性能共享存储计算机系统的新颖结构，具有简化的可制造性。计算机系统包含系统单元的重复，其中每个单元由处理器芯片和由本地存储器总线连接到处理器芯片的存储器子集（具有诸如DRAM或SRAM的存储器芯片）组成。节点间的独特类型将每个节点中的每个系统单元连接到同一节点中的每个其他单元。不同单元中的存储器子集不需要具有相同的大小，并且不同的节点不需要具有相同数量的单元。每个节点具有节点缓存，节点目录和节点电子交换机，以管理同一节点和不同节点中的所有小区之间的所有传输和数据一致性。计算机系统中的所有存储器子集的集合包括系统共享存储器，其中存储在任何存储器子集中的数据可由系统中的其他处理器芯片上的处理器访问。系统共享内存中的每个位置都有一个唯一的真实地址，可以由系统中的任何处理器使用。因此，可以在系统中的所有处理器的可执行指令中使用相同的存储器地址。节点目录自动管理计算机系统中所有处理器高速缓存中正在更改的所有数据的一致性，而不管数据存储在系统的共享存储器中的位置，无论系统中哪个单元包含处理器将数据更改为在计算机系统中的所有节点之间提供数据一致性。

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