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1. 发明授权

US4218740A Interface adaptor architecture 失效
标题翻译：接口适配器架构
公开(公告)号：US4218740A
公开(公告)日：1980-08-19
申请号：US757120
申请日：1977-01-05
申请人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , William D. Mensch, Jr. , Charles I. Peddle , Gene A. Schriber , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , William D. Mensch, Jr. , Charles I. Peddle , Gene A. Schriber , Michael F. Wiles
IPC分类号： G06F13/24 , G06F13/38 , G06F3/00
CPC分类号： G06F13/38 , G06F13/24
摘要： A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.The peripheral interface adaptor includes a plurality of system data bus buffer circuits coupled to a system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. The direction of data flow in the peripheral data bus is controlled by a data direction register. Data from the system data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register and the control register are transferred via an output bus to the system data bus buffers. Control signals are generated by select, read/write control, and register select logic which provides signals on a control bus coupled to the input register, the data register, the control register, and the data direction register to control data transfers between the various buses, registers, and buffer circuits.
摘要翻译：用于数据处理系统的外围接口适配器（PIA）电路包含存储器元件或控制寄存器，允许在程序控制下对PIA的逻辑功能进行修改。外围接口适配器包括耦合到系统数据总线的多个系统数据总线缓冲电路，并且还包括耦合到双向外围数据总线的外围接口缓冲电路。外围数据总线中数据流的方向由数据方向寄存器控制。来自系统数据总线缓冲器的数据被输入到输入寄存器中，并且从那里传送到耦合到控制寄存器，数据方向寄存器和数据寄存器的输入总线。来自外围数据总线，数据方向寄存器和控制寄存器的数据通过输出总线传送到系统数据总线缓冲器。控制信号由选择，读/写控制和寄存器选择逻辑产生，该逻辑在耦合到输入寄存器，数据寄存器，控制寄存器和数据方向寄存器的控制总线上提供信号，以控制各种总线之间的数据传输，寄存器和缓冲电路。

2. 发明授权

US4087855A Valid memory address enable system for a microprocessor system 失效
标题翻译：微处理器系统的有效存储器地址使能系统
公开(公告)号：US4087855A
公开(公告)日：1978-05-02
申请号：US614109
申请日：1975-09-17
申请人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
IPC分类号： G06F9/30 , G06F13/24 , G06F13/38 , G06F15/78 , H04L25/30 , G06F3/00 , G06F13/00
CPC分类号： G06F13/24 , G06F13/38
摘要： A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.
摘要翻译：数字系统包括耦合到数据总线和地址总线的微处理器。用于存储数据和指令的存储器连接到数据总线和地址总线。外围设备连接到接口适配器。接口适配器连接到数据总线和地址总线，并执行数字系统与外围设备（如打印机或显示设备）之间的接口功能。微处理器包括用于产生有效存储器地址（VMA）输出的逻辑电路。当地址总线上的二进制地址有效时，VMA输出用于产生施加到存储器和适配器的使能信号，以使存储器和适配器由微处理器访问，并防止存储器和适配器成为当地址总线上的二进制地址对微处理器无效时由微处理器访问。

3. 发明授权

US4020472A Master slave registers for interface adaptor 失效
标题翻译：接口适配器的主从寄存器
公开(公告)号：US4020472A
公开(公告)日：1977-04-26
申请号：US614114
申请日：1975-09-17
申请人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
IPC分类号： G06F13/24 , G06F13/38 , G06F3/00
CPC分类号： G06F13/38 , G06F13/24
摘要： An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data register, coupled to the input register by means of an internal input bus. Each of the plurality of registers includes flip-flops which are coupled as slave flip-flops to corresponding flip-flops of the input register. The corresponding flip-flops of the input register function as master flip-flops. The interface adaptor also includes register selection logic circuitry for selecting one of the plurality of registers by electrically coupling its slave flip-flop to the corresponding master flip-flops of the input register.
摘要翻译：适用于微处理器系统的接口适配器包括耦合到微处理器系统的双向数据总线的输入寄存器。接口适配器包括多个寄存器，包括通过内部输入总线耦合到输入寄存器的控制寄存器和数据寄存器。多个寄存器中的每一个包括作为从触发器耦合到输入寄存器的相应触发器的触发器。输入寄存器的相应触发器用作主触发器。接口适配器还包括寄存器选择逻辑电路，用于通过将其从触发器电耦合到输入寄存器的相应主触发器来选择多个寄存器中的一个。

4. 发明授权

US4263650A Digital data processing system with interface adaptor having programmable, monitorable control register therein 失效
标题翻译：具有接口适配器的数字数据处理系统，其中具有可编程的，可监控的控制寄存器
公开(公告)号：US4263650A
公开(公告)日：1981-04-21
申请号：US7752
申请日：1979-01-30
申请人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
IPC分类号： G06F13/24 , G06F13/38 , G06F3/04 , G06F9/00 , G06F13/00
CPC分类号： G06F13/24 , G06F13/38
摘要： A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.
摘要翻译：一种数字系统，包括多个金属氧化物半导体（MOS）芯片随机存取存储器（RAM），只读存储器（ROM）和耦合到公共双向数据总线的外围接口适配器，该公共双向数据总线耦合到微处理器单元（MPU）。每个外设接口适配器都包含一个可在程序控制下加载的控制寄存器。控制寄存器的内容控制接口适配器内几个寄存器的选择。控制寄存器还控制外围接口适配器的其他功能，包括确定接口适配器外围缓冲区中数据移动的方向。每个接口适配器的控制寄存器的内容可由微处理器单元监视。

5. 发明授权

US4086627A Interrupt system for microprocessor system 失效
标题翻译：微处理器系统中断系统
公开(公告)号：US4086627A
公开(公告)日：1978-04-25
申请号：US614110
申请日：1975-09-17
申请人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
IPC分类号： G06F9/30 , G06F13/24 , G06F13/38 , G06F15/78 , H04L25/30 , G06F9/18
CPC分类号： G06F13/24 , G06F13/38
摘要： A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device. The interrupt logic circuitry also stores status information indicative of the occurrence of the first interrupt signal and effects interrogation of that status via the data bus.
摘要翻译：微处理器系统包括微处理器，存储器和全部耦合到数据总线的接口适配器。接口适配器耦合在数据总线和外围设备之间，如电传打印机。第一个中断导体连接到外围设备，并中断接口适配器中的逻辑电路。第二个中断导体连接到微处理器和中断逻辑电路。中断逻辑电路也通过数据总线耦合到微处理器并可询问。中断逻辑电路存储来自数据总线的中断控制信息，并响应于存储的中断控制信息和由外围设备在第一中断导体上产生的中断信号，在第二中断导体上产生第二中断信号。中断逻辑电路还存储指示第一中断信号的出现的状态信息，并通过数据总线影响该状态的询问。

6. 发明授权

US4006457A Logic circuitry for selection of dedicated registers 失效
标题翻译：用于选择专用寄存器的逻辑电路
公开(公告)号：US4006457A
公开(公告)日：1977-02-01
申请号：US550338
申请日：1975-02-18
申请人： Edward C. Hepworth , Rodney J. Means , Charles I. Peddle
发明人： Edward C. Hepworth , Rodney J. Means , Charles I. Peddle
IPC分类号： G06F15/78 , H04Q9/00 , G11C17/00 , H04L5/00
CPC分类号： G06F15/7864
摘要： An MOS (Metal-Oxide-Semiconductor) integrated circuit includes four dedicated registers thereon, two of which are "write only" registers having the capability of being written into, but not read from, by means of buffer circuitry for coupling a bidirectional data bus to the dedicated registers. The other two dedicated registers are "read only" registers having the capability of being read from, but not written into, by means of the buffer circuitry. The integrated circuit chip is itself addressable by means of a plurality of address conductors of an address bus coupleable to the integrated circuit chip, and the four dedicated registers within the integrated circuit chip are further addressable by means of an additional address conductor called a register select address line. A control input conductor is coupled to the integrated circuit chip and is used to control the direction of data flow of the buffer circuitry and is also used in conjunction with the register select address line to select one of four dedicated registers. This provides the advantage of reducing the number of external connections required for the integrated circuit chip, and is possible only because the registers are dedicated.
摘要翻译： MOS（金属氧化物半导体）集成电路包括四个专用寄存器，其中两个是“只写入”寄存器，其具有通过用于耦合双向数据总线的缓冲电路写入但不从其读取的能力到专用寄存器。另外两个专用寄存器是具有通过缓冲电路读取但不写入的能力的“只读”寄存器。集成电路芯片本身可通过可与集成电路芯片耦合的地址总线的多个地址导体来寻址，并且集成电路芯片内的四个专用寄存器可通过称为寄存器选择的附加地址指令进一步寻址地址栏。控制输入导体耦合到集成电路芯片，并用于控制缓冲电路的数据流动方向，并结合寄存器选择地址线选择四个专用寄存器之一。这提供了减少集成电路芯片所需的外部连接数量的优点，并且可能仅仅是因为寄存器是专用的。

7. 发明授权

US3975712A Asynchronous communication interface adaptor 失效
标题翻译：异步通信接口适配器
公开(公告)号：US3975712A
公开(公告)日：1976-08-17
申请号：US550336
申请日：1975-02-18
申请人： Edward C. Hepworth , Rodney J. Means , Charles I. Peddle
发明人： Edward C. Hepworth , Rodney J. Means , Charles I. Peddle
IPC分类号： H03M7/00 , G06F13/00 , G06F13/38 , G06F15/16 , G06F15/177 , H04L13/06 , H04L25/30 , G06F3/00 , H04J3/00 , H04Q5/00
CPC分类号： G06F13/38
摘要： An integrated circuit asynchronous communications interface adapter (ACIA) includes circuitry on a semiconductor chip for interfacing with a bidirectional data bus of a microcomputer. Bus interface circuitry on the ACIA chip controls data transfer between the microcomputer data bus and a transmit data register and a read data register on the ACIA chip. Transmitting circuitry on the ACIA chip converts data from a parallel format to a serial format. Receiving circuitry on the ACIA chip accepts data in a serial format and converts it to a parallel format prior to transferring it to a receive data register. A control register controls data transfer throughout the ACIA chip. A status register on the ACIA chip may be interrogated under program control to determine the status of registers and/or correctness of data format, status of interrupt logic or modem control lines. Several Modem and/or peripheral control functions, including a "clear-to-send" input, a "request-to-send" output and a "data-carrier-loss detected" input are provided by circuitry on the ACIA chip.
摘要翻译：集成电路异步通信接口适配器（ACIA）包括用于与微型计算机的双向数据总线接口的半导体芯片上的电路。 ACIA芯片上的总线接口电路控制微机数据总线与发送数据寄存器之间的数据传输以及ACIA芯片上的读取数据寄存器。 ACIA芯片上的发送电路将数据从并行格式转换为串行格式。 ACIA芯片上的接收电路以串行格式接收数据，并将其转换为并行格式，然后将其传输到接收数据寄存器。控制寄存器控制整个ACIA芯片的数据传输。可以在程序控制下询问ACIA芯片上的状态寄存器，以确定寄存器的状态和/或数据格式的正确性，中断逻辑或调制解调器控制线的状态。包括“清除发送”输入，“请求发送”输出和“数据载波丢失检测”输入的多个调制解调器和/或外设控制功能由ACIA芯片上的电路提供。

8. 发明授权

US08122319B2 Page-based failure management for flash memory 有权
标题翻译：基于页面的闪存故障管理
公开(公告)号：US08122319B2
公开(公告)日：2012-02-21
申请号：US11657935
申请日：2007-01-24
申请人： Charles I. Peddle
发明人： Charles I. Peddle
IPC分类号： G11C29/00
CPC分类号： G11C29/88
摘要： A page-based failure management system for flash memory includes at least one flash memory device which includes at least one page and at least one operable page. The system also includes an indication of operability of the at least one page in the at least one flash device.
摘要翻译：用于闪存的基于页面的故障管理系统包括至少一个包括至少一个页面和至少一个可操作页面的闪存设备。该系统还包括至少一个闪光装置中的至少一个页面的可操作性的指示。

9. 发明申请

US20080177956A1 Page-based failure management for flash memory 有权
标题翻译：基于页面的闪存故障管理
公开(公告)号：US20080177956A1
公开(公告)日：2008-07-24
申请号：US11657935
申请日：2007-01-24
申请人： Charles I. Peddle
发明人： Charles I. Peddle
IPC分类号： G06F12/00
CPC分类号： G11C29/88
摘要： A page-based failure management system for flash memory includes at least one flash memory device which includes at least one page and at least one operable page. The system also includes an indication of operability of the at least one page in the at least one flash device.
摘要翻译：用于闪存的基于页面的故障管理系统包括至少一个包括至少一个页面和至少一个可操作页面的闪存设备。该系统还包括至少一个闪光装置中的至少一个页面的可操作性的指示。

10. 发明授权

US10204040B2 High speed flash controllers 有权
公开(公告)号：US10204040B2
公开(公告)日：2019-02-12
申请号：US15298074
申请日：2016-10-19
申请人： Charles I. Peddle
发明人： Charles I. Peddle
IPC分类号： G06F11/00 , G06F12/02 , G06F11/10 , G06F13/40 , G11C29/52 , G06F13/28 , G06F13/16 , G06F12/1081 , G06F13/42
摘要： A high speed USB memory controller includes a microprocessor, flash memory, memory buffers directly accessible to the microprocessor and flash memory, and a USB interface for writing data directly into the memory buffers. This allows devices with multiple flash die to operate at full bus speed.

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