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1. 发明授权

US5359715A Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces 失效
标题翻译：具有多个处理器，多个系统总线和多个I / O总线的计算机系统架构，通过多个端口接口连接
公开(公告)号：US5359715A
公开(公告)日：1994-10-25
申请号：US760786
申请日：1991-09-16
申请人： Thomas F. Heil , Craig A. Walrath , Jimmy D. Pike , Edward A. McDonald , Arthur F. Cochcroft, Jr. , P. Chris Raeuber , Daniel C. Robbins , Gene F. Young
发明人： Thomas F. Heil , Craig A. Walrath , Jimmy D. Pike , Edward A. McDonald , Arthur F. Cochcroft, Jr. , P. Chris Raeuber , Daniel C. Robbins , Gene F. Young
IPC分类号： G06F15/16 , G06F13/24 , G06F13/36 , G06F15/177 , G06F13/00
CPC分类号： G06F13/24
摘要： Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.
摘要翻译：多处理器系统被配置为包括至少两个系统或存储器总线，其中至少两个处理器耦合到每个系统总线，以及耦合到系统总线的至少两个I / O总线，以提供多个扩展槽，为每个I / O总线以单个系统总线负载为代价的系统的相应数量的I / O总线代理。系统和I / O总线中的每一个被独立地仲裁以定义用于本发明的多个处理器系统的解耦总线系统。用于系统的主存储器由至少两个存储器交错组成，每个存储器交错可以通过系统总线同时访问。每个I / O总线通过I / O接口电路连接到系统总线，I / O接口电路缓冲写入主存储器的数据或由I / O总线代理器读取存储器交错的数据。

2. 发明授权

US5327540A Method and apparatus for decoding bus master arbitration levels to optimize memory transfers 失效
标题翻译：用于解码总线主控仲裁级别以优化存储器传输的方法和装置
公开(公告)号：US5327540A
公开(公告)日：1994-07-05
申请号：US16652
申请日：1993-02-01
申请人： Thomas F. Heil , Daniel C. Robbins , Edward A. McDonald
发明人： Thomas F. Heil , Daniel C. Robbins , Edward A. McDonald
IPC分类号： G06F13/362
CPC分类号： G06F13/362
摘要： A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique four-bit Micro Channel arbitration values assigned to the bus masters to retrieve buffer configuration parameters stored within a register file containing different configuration parameters for each bus master. The data buffer is dynamically configured for optimal performance with each bus master having control of the Micro Channel bus in accordance with the parameter data retrieved from the register file.
摘要翻译：一种用于在计算机系统内优化配置数据缓冲器的缓冲器管理方案，其包括通过微通道总线连接的多个总线主机和数据缓冲器到诸如存储器之类的共享资源。该方案解码分配给总线主机的唯一的四位微通道仲裁值，以检索存储在每个总线主机的不同配置参数的寄存器文件中的缓冲区配置参数。根据从寄存器文件检索的参数数据，数据缓冲区被动态地配置为具有最佳性能，每个总线主机具有对微通道总线的控制。

3. 发明授权

US5418914A Retry scheme for controlling transactions between two busses 失效
标题翻译：用于控制两台总线之间的交易的重试方案
公开(公告)号：US5418914A
公开(公告)日：1995-05-23
申请号：US143393
申请日：1993-10-25
申请人： Thomas F. Heil , Edward A. McDonald , Gene F. Young , Craig A. Walrath , James M. Ottinger , Marti D. Miller
发明人： Thomas F. Heil , Edward A. McDonald , Gene F. Young , Craig A. Walrath , James M. Ottinger , Marti D. Miller
IPC分类号： G06F13/36 , G06F13/362
CPC分类号： G06F13/362
摘要： A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource. Upon negation of the busy signal, all bus masters will be permitted to compete for ownership of the bus.
摘要翻译：一种用于优化在计算机系统中使用第一总线的重试方案，该计算机系统包括通过第一总线连接到接口电路和第二总线的多个总线主机。接口电路包括当第二总线处于忙状态时产生忙信号的逻辑和当第二总线处于忙状态时当总线主机寻址接口电路时产生重试信号的逻辑。每个总线主机包括用于在从接口电路接收到重试信号时接收重试信号和放弃公共总线的控制的逻辑。总线仲裁器包括用于接收忙信号的逻辑，并且阻止任何总线主机寻求访问第二总线参与用于控制公共第一总线的仲裁，直到忙信号被否定为止。因此，在忙信号期间，第一总线可以由不需要访问共享资源的任何总线主控器来控制。在否定忙碌信号后，所有巴士主人将被允许竞争总线的所有权。

4. 发明授权

US06098113A Apparatus and method for address translation and allocation for a plurality of input/output (I/O) buses to a system bus 失效
标题翻译：用于多个输入/输出（I / O）总线到系统总线的地址转换和分配的装置和方法
公开(公告)号：US06098113A
公开(公告)日：2000-08-01
申请号：US417701
申请日：1995-04-06
申请人： Thomas F. Heil , Edward A. McDonald , James M. Ottinger , Jeffrey A. Hawkey
发明人： Thomas F. Heil , Edward A. McDonald , James M. Ottinger , Jeffrey A. Hawkey
IPC分类号： G06F13/42 , G06F3/00
CPC分类号： G06F13/423
摘要： Multiple subsystem I/O (Input/Output) buses are coupled to one or more system buses of a computer system by interface circuits which perform necessary decoding of memory space and I/O (Input/Output) space for allocation of portions of the memory space and the I/O (Input/Output) space to each I/O (Input/Output) bus. The interface circuits also translate fixed addresses within each I/O (Input/Output) bus to permit proper operation of the I/O (Input/Output) buses with the computer system. The interface circuits are programmed by the computer system to define the allocated memory spaces and I/O (Input/Output) spaces for the corresponding I/O (Input/Output) buses. Programming of the I/O (Input/Output) buses is performed at the time of system configuration by writing appropriate values into configuration registers incorporated into each of the interface circuits.
摘要翻译：多个子系统I / O（输入/输出）总线通过接口电路耦合到计算机系统的一个或多个系统总线，所述接口电路执行存储器空间的必要解码以及用于分配存储器部分的I / O（输入/输出）空间和每个I / O（输入/输出）总线的I / O（输入/输出）空间。接口电路还可以转换每个I / O（输入/输出）总线中的固定地址，以允许计算机系统正确操作I / O（输入/输出）总线。接口电路由计算机系统编程，以便为相应的I / O（输入/输出）总线定义分配的存储空间和I / O（输入/输出）空间。通过将合适的值写入并入每个接口电路的配置寄存器中，在系统配置时执行I / O（输入/输出）总线的编程。

5. 发明授权

US5269005A Method and apparatus for transferring data within a computer system 失效
标题翻译：用于在计算机系统内传送数据的方法和装置
公开(公告)号：US5269005A
公开(公告)日：1993-12-07
申请号：US761185
申请日：1991-09-17
申请人： Thomas F. Heil , Edward A. McDonald , Gene F. Young
发明人： Thomas F. Heil , Edward A. McDonald , Gene F. Young
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： In a processing system any response to an interrupt acknowledge cycle is deferred until the transfer of buffered data to be written from an agent on a subsystem I/O bus to main memory of the system is assured. To expedite system operation, data to be written to main memory by an agent on an I/O bus is buffered in an interface circuit. As soon as the data is buffered, the I/O bus agent is released and interrupts a processor on the system bus indicating completion of the data write. A tightly coupled interrupt controller is used so that the agent does not need to own the I/O or system bus to generate the interrupt. The interrupted processor issues an interrupt acknowledge (IAK) cycle on the system bus to receive an interrupt vector from the interrupt controller. The interface circuit recognizes the IAK cycle and generates a retry signal for the processor if buffered data remains in the interface circuit. In response to the retry signal, the processor is taken off the system bus and not allowed to regain the system bus until the buffered data is written to main memory. A bus busy signal is raised and will not be lowered until the data is written to main memory. When the busy signal is lowered, the processor regains the system bus and receives an interrupt vector from the interrupt controller. I/O bus ownership is locked until the interrupted processor has received an interrupt vector and the IAK cycle is complete. If no buffered data remains in the interface circuit, no retry signal is generated. The interrupt controller waits a predefined period of time for a retry signal and if none is detected, the interrupt controller issues an appropriate interrupt vector to complete the IAK cycle. For multiple I/O buses, preferably only one interface circuit retries processors issuing IAK cycles.
摘要翻译：在处理系统中，对中断确认周期的任何响应都被推迟，直到将从子系统I / O总线上的代理写入缓冲数据传送到系统的主存储器得到保证。为了加快系统运行，由I / O总线上的代理程序写入主存的数据被缓存在接口电路中。一旦数据被缓冲，I / O总线代理被释放并中断系统总线上的处理器，指示完成数据写入。使用紧密耦合的中断控制器，以便代理不需要拥有I / O或系统总线来产生中断。中断的处理器在系统总线上发出中断确认（IAK）周期，以从中断控制器接收中断向量。接口电路识别IAK周期，并且如果缓冲数据保留在接口电路中，则为处理器生成重试信号。响应于重试信号，处理器从系统总线中取出，不允许重新获得系统总线，直到缓冲的数据被写入主存储器。总线忙信号升高，直到数据写入主存储器才会降低。当忙信号降低时，处理器恢复系统总线并从中断控制器接收中断向量。 I / O总线所有权被锁定，直到中断处理器收到中断向量并且IAK周期完成。如果接口电路中没有缓冲的数据，则不会产生重试信号。中断控制器等待重试信号的预定义时间段，如果没有检测到，中断控制器发出适当的中断向量来完成IAK周期。对于多个I / O总线，最好只有一个接口电路重试发出IAK周期的处理器。

6. 发明授权

US09466877B2 Hospital bed having near field communication capability 有权
标题翻译：医院床具有近场通信能力
公开(公告)号：US09466877B2
公开(公告)日：2016-10-11
申请号：US13687005
申请日：2012-11-28
申请人： Steven A. Dixon , Keith A. Huster , Irvin J. Vanderpohl, III , Thomas F. Heil , Richard J. Schuman , Christopher K. Lack
发明人： Steven A. Dixon , Keith A. Huster , Irvin J. Vanderpohl, III , Thomas F. Heil , Richard J. Schuman , Christopher K. Lack
IPC分类号： H01Q1/12 , H01Q1/44 , H01Q1/00 , A61B5/00
CPC分类号： G08B23/00 , A61B5/002 , A61B5/6891 , H01Q1/007 , H01Q1/44 , H04B5/0031 , H04B5/0056 , H04B5/0093 , H04L67/104 , H04W4/80
摘要： An apparatus for providing data communication and power to a device located in a room having a power outlet is disclosed. The power outlet may be a standard AC outlet, for example. The apparatus includes a cable extending from the device and having a plug comprising a plug body. Prongs extend from the plug body and couple to the power outlet to receive power. A first near field communication antenna is carried by the plug body. A communication module has a second near field communication antenna and is located in the room in proximity to the plug. At least one of the first near field communication antenna and the second near field communication antenna communicates data wirelessly to the other of the first near field communication antenna and the second near field communication antenna.
摘要翻译：公开了一种用于向位于具有电源插座的房间中的设备提供数据通信和电力的设备。例如，电源插座可以是标准AC插座。该设备包括从该设备延伸并且具有包括塞体的插头的电缆。叉头从插头体延伸并耦合到电源插座以接收电力。第一近场通信天线由插头体承载。通信模块具有第二近场通信天线，并且位于靠近插头的房间中。第一近场通信天线和第二近场通信天线中的至少一个将数据无线地传送到第一近场通信天线和第二近场通信天线中的另一个。

7. 发明申请

US20110247135A1 SIDERAIL POWER COMMUNICATION INTERFACE 有权
标题翻译： SIDERAIL电源通信接口
公开(公告)号：US20110247135A1
公开(公告)日：2011-10-13
申请号：US12757233
申请日：2010-04-09
申请人： Fred Herman , Thomas F. Heil , Charles A. Howell
发明人： Fred Herman , Thomas F. Heil , Charles A. Howell
IPC分类号： A47C21/08
CPC分类号： A61G7/0507 , A47C21/08 , A61G7/0509 , A61G7/0514 , A61G7/0524
摘要： A siderail assembly for a person support apparatus comprises a siderail body, a grip portion, and a power communication device. The siderail body includes a front surface, a back surface, and a side surface extending between the front surface and the back surface. The side surface defines a perimeter of the siderail body. The grip portion includes a siderail opening through a portion of the siderail body. The grip opening has an upper grip opening portion that cooperates with the side surface to define a grip. The power communication device is configured to communicate power wirelessly to a device in communication therewith.
摘要翻译：用于人员支撑装置的座椅组件包括一个座椅主体，一个把手部分和一个动力通讯装置。座椅主体包括前表面，后表面和在前表面和后表面之间延伸的侧表面。侧表面限定了赛车身体的周长。把手部分包括穿过该挡板主体的一部分的一个侧栏开口。抓握开口具有与侧表面配合以限定抓握的上抓握开口部分。电力通信设备被配置为与通信的设备无线地通信电力。

8. 发明授权

US5502824A Peripheral component interconnect "always on" protocol 失效
标题翻译：外围组件互连“始终开启”协议
公开(公告)号：US5502824A
公开(公告)日：1996-03-26
申请号：US997427
申请日：1992-12-28
申请人： Thomas F. Heil
发明人： Thomas F. Heil
IPC分类号： G06F13/364 , G06F13/42
CPC分类号： G06F13/364 , G06F13/4217
摘要： A Peripheral Component Interconnect (PCI) bus has a protocol that guarantees that at all times, except for turn-around clocks necessary to prevent contention, that the bus is actively driven to a logic 1 or 0 by some device attached thereto. As long as all devices attached to the bus are compliant with the specification, the bus will never be left floating for long intervals, and thus the system designer is free to eliminate the pull-up resistors typically required on other buses.
摘要翻译：外围组件互连（PCI）总线具有一种协议，其保证除了为了防止争用而需要的周转时钟之外，总是被附加到其上的某个设备主动地驱动到逻辑1或0。只要连接到总线的所有设备符合规范，总线将永远不会长时间悬空，因此系统设计人员可以自由消除其他总线上通常需要的上拉电阻。

9. 发明授权

US5343478A Computer system configuration via test bus 失效
标题翻译：通过测试总线进行计算机系统配置
公开(公告)号：US5343478A
公开(公告)日：1994-08-30
申请号：US800901
申请日：1991-11-27
申请人： Larry C. James , Carl W. Kagy , Jeffrey F. Gates , Jeffrey A. Hawkey , Thomas F. Heil , David L. Simpson
发明人： Larry C. James , Carl W. Kagy , Jeffrey F. Gates , Jeffrey A. Hawkey , Thomas F. Heil , David L. Simpson
IPC分类号： G01R31/3185 , G06F11/00 , G06F11/22 , G06F11/30 , G01R31/28
CPC分类号： G01R31/318552 , G06F11/2205
摘要： System configuration, monitoring and control functions are performed in a computer system by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct one or more modules of the system. The conventional serial test bus is modified to include register circuitry on modules of the computer system and/or within integrated circuits which are interconnected to construct the modules. These registers are written and read by the serial test bus for configuring the computer system as well as performing other operations such as monitoring and error logging within the computer system. To extend the amount of information which can be contained within these registers, preferably memory devices such as EEPROM, RAM, and the like, are associated with the registers and accessible therethrough. The introduction of memory into the serial test bus permits configuration information to be stored in the modules and/or integrated circuits making up the computer system. If memory and/or other devices external to the serial test bus are included on modules or other components of the system, the time required to access these devices may exceed a default access time defined by the operating speed of the serial test bus. To ensure proper operation with such devices, a pacing or ready signal is generated such that access is delayed until the requested access can be successfully completed.
摘要翻译：系统配置，监视和控制功能在计算机系统中通过串行测试总线来执行，该串行测试总线被并入计算机系统中，用于测试用于构建系统的一个或多个模块的组件，例如集成电路。传统的串行测试总线被修改为在计算机系统的模块上和/或在互连以构成模块的集成电路内包括寄存器电路。这些寄存器由串行测试总线写入和读取，用于配置计算机系统，以及执行其他操作，如计算机系统中的监视和错误记录。为了扩展可以包含在这些寄存器中的信息量，优选地，诸如EEPROM，RAM等的存储器件与寄存器相关联并且可以通过其访问。将存储器引入串行测试总线允许将配置信息存储在构成计算机系统的模块和/或集成电路中。如果串行测试总线外部的存储器和/或其他设备包含在系统的模块或其他组件上，则访问这些设备所需的时间可能会超过由串行测试总线的运行速度定义的默认访问时间。为了确保使用这些设备的正常操作，生成起搏或准备就绪信号，使得访问被延迟，直到请求的访问成功完成。

10. 发明申请

US20130135160A1 HOSPITAL BED HAVING NEAR FIELD COMMUNICATION CAPABILITY 有权
标题翻译：具有近场通信能力的医院病床
公开(公告)号：US20130135160A1
公开(公告)日：2013-05-30
申请号：US13687005
申请日：2012-11-28
申请人： Steven A. Dixon , Keith A. Huster , Irvin J. Vanderpohl, III , Thomas F. Heil , Richard J. Schuman , Christopher K. Lack
发明人： Steven A. Dixon , Keith A. Huster , Irvin J. Vanderpohl, III , Thomas F. Heil , Richard J. Schuman , Christopher K. Lack
IPC分类号： H01Q1/44
CPC分类号： G08B23/00 , A61B5/002 , A61B5/6891 , H01Q1/007 , H01Q1/44 , H04B5/0031 , H04B5/0056 , H04B5/0093 , H04L67/104 , H04W4/80
摘要： An apparatus for providing data communication and power to a device located in a room having a power outlet is disclosed. The power outlet may be a standard AC outlet, for example. The apparatus includes a cable extending from the device and having a plug comprising a plug body. Prongs extend from the plug body and couple to the power outlet to receive power. A first near field communication antenna is carried by the plug body. A communication module has a second near field communication antenna and is located in the room in proximity to the plug. At least one of the first near field communication antenna and the second near field communication antenna communicates data wirelessly to the other of the first near field communication antenna and the second near field communication antenna.
摘要翻译：公开了一种用于向位于具有电源插座的房间中的设备提供数据通信和电力的设备。例如，电源插座可以是标准AC插座。该设备包括从该设备延伸并且具有包括塞体的插头的电缆。叉头从插头体延伸并耦合到电源插座以接收电力。第一近场通信天线由插头体承载。通信模块具有第二近场通信天线，并且位于靠近插头的房间中。第一近场通信天线和第二近场通信天线中的至少一个将数据无线地传送到第一近场通信天线和第二近场通信天线中的另一个。

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