专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6012127A Multiprocessor computing apparatus with optional coherency directory 失效
标题翻译：具有可选一致性目录的多处理器计算设备
公开(公告)号：US6012127A
公开(公告)日：2000-01-04
申请号：US989371
申请日：1997-12-12
申请人： Edward A. McDonald , James M. Ottinger , Harry W. Scrivener, III
发明人： Edward A. McDonald , James M. Ottinger , Harry W. Scrivener, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A multiprocessor computing apparatus including a plurality of processors each having a cache memory and preferably arranged in nodes on a system bus. A first cache coherency providing mechanism coupled to the processors for achieving system level cache coherency. A second cache coherency providing mechanism is also provided. When an error is detected in the first cache coherency providing mechanism, this mechanism is disabled and cache coherency is achieved by the second cache coherency providing mechanism. In a preferred embodiment, the first mechanism includes coherency directories and the second mechanism includes bus snooping.
摘要翻译：一种多处理器计算装置，包括多个处理器，每个处理器具有高速缓冲存储器，并且优选地布置在系统总线上的节点中。耦合到处理器的第一高速缓存一致性提供机制，用于实现系统级高速缓存一致性。还提供了第二高速缓存一致性提供机制。当在第一高速缓存一致性提供机制中检测到错误时，该机制被禁用，并且由第二高速缓存一致性提供机制实现高速缓存一致性。在优选实施例中，第一机制包括相干目录，第二机制包括总线监听。

2. 发明授权

US06202137B1 Method and apparatus of arbitrating requests to a multi-banked memory using bank selects 失效
标题翻译：使用银行选择将请求仲裁到多存储存储器的方法和装置
公开(公告)号：US06202137B1
公开(公告)日：2001-03-13
申请号：US08932521
申请日：1997-09-18
申请人： James M. Ottinger
发明人： James M. Ottinger
IPC分类号： G06F1200
CPC分类号： G06F13/1647
摘要： A present request includes a present bank select that maps the present request to one bank of a memory having multiple banks. A first request includes a first bank select that maps the first request to one bank of the memory, and a second request includes a second bank select that maps the second request to one bank of the memory. A method of arbitrating requests to the memory includes the steps of (a) processing a present request to access the memory; (b) receiving a first request to access the memory and a second request to access the memory; (c) selecting from the first request and the second request, a next request to access the memory; and (d) processing the next request to access the memory. Furthermore, the selecting step of the method is dependent upon the present bank select, the first bank select, and the second bank select. A memory controller and a computer system which implement the method of arbitrating requests is also disclosed.
摘要翻译：当前请求包括将当前请求映射到具有多个存储体的存储器的一个存储体的当前存储体选择。第一请求包括将第一请求映射到存储器的一个存储体的第一存储体选择，并且第二请求包括将第二请求映射到存储器的一个存储体的第二存储体选择。向存储器仲裁请求的方法包括以下步骤：（a）处理访问存储器的当前请求; （b）接收访问所述存储器的第一请求和访问所述存储器的第二请求; （c）从第一请求和第二请求中选择接入存储器的下一个请求; 和（d）处理访问存储器的下一个请求。此外，该方法的选择步骤取决于当前存储体选择，第一组选择和第二组选择。还公开了一种实现仲裁请求的方法的存储器控制器和计算机系统。

3. 发明授权

US5418914A Retry scheme for controlling transactions between two busses 失效
标题翻译：用于控制两台总线之间的交易的重试方案
公开(公告)号：US5418914A
公开(公告)日：1995-05-23
申请号：US143393
申请日：1993-10-25
申请人： Thomas F. Heil , Edward A. McDonald , Gene F. Young , Craig A. Walrath , James M. Ottinger , Marti D. Miller
发明人： Thomas F. Heil , Edward A. McDonald , Gene F. Young , Craig A. Walrath , James M. Ottinger , Marti D. Miller
IPC分类号： G06F13/36 , G06F13/362
CPC分类号： G06F13/362
摘要： A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource. Upon negation of the busy signal, all bus masters will be permitted to compete for ownership of the bus.
摘要翻译：一种用于优化在计算机系统中使用第一总线的重试方案，该计算机系统包括通过第一总线连接到接口电路和第二总线的多个总线主机。接口电路包括当第二总线处于忙状态时产生忙信号的逻辑和当第二总线处于忙状态时当总线主机寻址接口电路时产生重试信号的逻辑。每个总线主机包括用于在从接口电路接收到重试信号时接收重试信号和放弃公共总线的控制的逻辑。总线仲裁器包括用于接收忙信号的逻辑，并且阻止任何总线主机寻求访问第二总线参与用于控制公共第一总线的仲裁，直到忙信号被否定为止。因此，在忙信号期间，第一总线可以由不需要访问共享资源的任何总线主控器来控制。在否定忙碌信号后，所有巴士主人将被允许竞争总线的所有权。

4. 发明授权

US06098113A Apparatus and method for address translation and allocation for a plurality of input/output (I/O) buses to a system bus 失效
标题翻译：用于多个输入/输出（I / O）总线到系统总线的地址转换和分配的装置和方法
公开(公告)号：US06098113A
公开(公告)日：2000-08-01
申请号：US417701
申请日：1995-04-06
申请人： Thomas F. Heil , Edward A. McDonald , James M. Ottinger , Jeffrey A. Hawkey
发明人： Thomas F. Heil , Edward A. McDonald , James M. Ottinger , Jeffrey A. Hawkey
IPC分类号： G06F13/42 , G06F3/00
CPC分类号： G06F13/423
摘要： Multiple subsystem I/O (Input/Output) buses are coupled to one or more system buses of a computer system by interface circuits which perform necessary decoding of memory space and I/O (Input/Output) space for allocation of portions of the memory space and the I/O (Input/Output) space to each I/O (Input/Output) bus. The interface circuits also translate fixed addresses within each I/O (Input/Output) bus to permit proper operation of the I/O (Input/Output) buses with the computer system. The interface circuits are programmed by the computer system to define the allocated memory spaces and I/O (Input/Output) spaces for the corresponding I/O (Input/Output) buses. Programming of the I/O (Input/Output) buses is performed at the time of system configuration by writing appropriate values into configuration registers incorporated into each of the interface circuits.
摘要翻译：多个子系统I / O（输入/输出）总线通过接口电路耦合到计算机系统的一个或多个系统总线，所述接口电路执行存储器空间的必要解码以及用于分配存储器部分的I / O（输入/输出）空间和每个I / O（输入/输出）总线的I / O（输入/输出）空间。接口电路还可以转换每个I / O（输入/输出）总线中的固定地址，以允许计算机系统正确操作I / O（输入/输出）总线。接口电路由计算机系统编程，以便为相应的I / O（输入/输出）总线定义分配的存储空间和I / O（输入/输出）空间。通过将合适的值写入并入每个接口电路的配置寄存器中，在系统配置时执行I / O（输入/输出）总线的编程。

5. 发明授权

US06553467B1 Bank information pre-decode apparatus 失效
标题翻译：银行信息预解码装置
公开(公告)号：US06553467B1
公开(公告)日：2003-04-22
申请号：US08909809
申请日：1997-08-12
申请人： James M. Ottinger
发明人： James M. Ottinger
IPC分类号： G06F1200
CPC分类号： G11C11/4087 , G06F13/1642
摘要： An apparatus for accelerating the speed of memory access cycles in a multi-bank memory. The apparatus includes decode logic that pre-decodes bank information from a requested address signal while the corresponding request is queued in the request queue. The pre-decode logic is propagated to the memory controller, preferably by re-insertion into the request queue, to facilitate more rapid memory accesses.
摘要翻译：一种用于加速多存储器存储器中的存储器存取周期速度的装置。该装置包括解码逻辑，该解码逻辑从所请求的地址信号中对存储体信息进行预解码，同时相应的请求在请求队列中排队。预解码逻辑被传播到存储器控制器，优选地通过重新插入到请求队列中，以便于更快速的存储器访问。

6. 发明授权

US6073216A System and method for reliable system shutdown after coherency corruption 失效
标题翻译：一致性损坏后可靠系统关机的系统和方法
公开(公告)号：US6073216A
公开(公告)日：2000-06-06
申请号：US980882
申请日：1997-11-25
申请人： Edward A. McDonald , James M. Ottinger , Harry W. Scrivener
发明人： Edward A. McDonald , James M. Ottinger , Harry W. Scrivener
IPC分类号： G06F11/07 , G06F11/10 , G06F12/08
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0817 , G06F11/1064
摘要： There is disclosed a memory control circuit for use in a processing system containing a plurality of processors coupled to a main memory by a common bus. The memory control circuit is adapted for implementing directory-based coherency in the processing system according to a selected coherency algorithm and comprises: 1) monitoring circuitry for detecting coherency corruption in a coherency directory associated with the main memory; and 2) coherency control circuitry responsive to a detection of coherency corruption in the coherency directory for dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner. In some embodiments, the monitoring circuitry further detects possible system coherency failure conditions external to the coherency directory and the coherency control circuitry responds to the detection of a possible system coherency failure condition by dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner.
摘要翻译：公开了一种用于处理系统中的存储器控制电路，该处理系统包含通过公共总线耦合到主存储器的多个处理器。存储器控制电路适于根据所选择的一致性算法在处理系统中实现基于目录的一致性，并且包括：1）监视电路，用于检测与主存储器相关联的一致性目录中的一致性损坏; 以及2）相干性控制电路，其响应于所述一致性目录中的一致性损坏的检测，以动态地修改所选择的一致性算法，从而使所述处理系统能够以受控的方式关闭。在一些实施例中，监视电路还检测相干目录外的可能的系统一致性故障条件，并且一致性控制电路通过动态地修改所选择的一致性算法来响应可能的系统一致性故障条件的检测，从而使处理系统能够关闭以受控的方式下来。

7. 发明授权

US6070231A Method and apparatus for processing memory requests that require coherency transactions 失效
标题翻译：用于处理需要一致性事务的存储器请求的方法和装置
公开(公告)号：US6070231A
公开(公告)日：2000-05-30
申请号：US982446
申请日：1997-12-02
申请人： James M. Ottinger
发明人： James M. Ottinger
IPC分类号： G06F12/08
CPC分类号： G06F12/0828
摘要： A method for processing memory requests and a memory controller that implements the method are disclosed. The method includes the steps of (a) receiving a first memory request from a first bus, (b) issuing a first coherency request on a second bus in order to process the first memory request, (c) storing the first coherency request in a storage area of the memory controller that is configured to receive memory requests from the second bus, and (d) processing the first coherency request from the storage area.
摘要翻译：公开了一种处理存储器请求的方法和实现该方法的存储器控制器。该方法包括以下步骤：（a）从第一总线接收第一存储器请求，（b）在第二总线上发布第一相关性请求以处理第一存储器请求;（c）将第一相关性请求存储在所述存储器控制器的存储区域被配置为从所述第二总线接收存储器请求，以及（d）从所述存储区域处理所述第一一致性请求。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式