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1. 发明授权

US06458678B1 Transistor formed using a dual metal process for gate and source/drain region 失效
标题翻译：晶体管使用双金属工艺形成栅极和源极/漏极区域
公开(公告)号：US06458678B1
公开(公告)日：2002-10-01
申请号：US09625130
申请日：2000-07-25
申请人： Thomas E. Spikes, Jr. , Frederick N. Hause , David D. Wu
发明人： Thomas E. Spikes, Jr. , Frederick N. Hause , David D. Wu
IPC分类号： H01L213205
CPC分类号： H01L29/66507 , H01L21/823814 , H01L21/823842 , H01L29/665
摘要： A method for forming a semiconductor device includes providing a substrate and forming a gate stack on the substrate. The gate stack includes a gate electrode having a thickness. Source/drain regions are formed in the substrate proximate the gate stack, and a first metal silicide layer is formed over the source drain regions. The thickness of the gate electrode is reduced, and a second metal silicide layer is formed over the reduced thickness gate electrode.
摘要翻译：一种形成半导体器件的方法包括提供衬底并在衬底上形成栅叠层。栅极堆叠包括具有厚度的栅电极。源极/漏极区域形成在靠近栅极堆叠的衬底中，并且在源极漏极区域上形成第一金属硅化物层。栅电极的厚度减小，并且在厚度较薄的栅电极上形成第二金属硅化物层。

2. 发明授权

US6037244A Method of manufacturing a semiconductor device using advanced contact formation 失效
标题翻译：使用高级接触形成制造半导体器件的方法
公开(公告)号：US6037244A
公开(公告)日：2000-03-14
申请号：US821660
申请日：1997-03-19
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
IPC分类号： H01L21/768 , H01L21/28 , H01L21/31
CPC分类号： H01L21/76895 , H01L21/76807
摘要： A method of forming a semiconductor device by using a pillar to form a contact with an active region of the device. A semiconductor device is formed by forming one or more active regions on a substrate of the semiconductor device and forming a pillar over at least a portion of one of the active regions. An insulating film selective to the pillar is provided over portions of the substrate adjacent the pillar. The pillar is then used to form a conductive contact with the active region over which it is formed. In one embodiment, the pillar is formed from a photoresist, while in other embodiments, the pillar is formed from a conductor material such as a metal. The active region may form a source/drain region or a gate electrode.
摘要翻译：一种通过使用柱形成与器件的有源区的接触形成半导体器件的方法。通过在半导体器件的衬底上形成一个或多个有源区并在一个有源区的至少一部分上形成柱来形成半导体器件。在基板的邻近柱的部分上设置对柱子有选择性的绝缘膜。然后使用该柱与其形成的有源区形成导电接触。在一个实施例中，柱由光致抗蚀剂形成，而在其它实施例中，柱由诸如金属的导体材料形成。有源区可以形成源/漏区或栅电极。

3. 发明授权

US06326251B1 Method of making salicidation of source and drain regions with metal gate MOSFET 有权
标题翻译：用金属栅极MOSFET对源极和漏极区域进行腐蚀的方法
公开(公告)号：US06326251B1
公开(公告)日：2001-12-04
申请号：US09290790
申请日：1999-01-12
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Thomas E. Spikes, Jr.
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28079 , H01L21/28088 , H01L21/823814 , H01L21/823835 , H01L29/495 , H01L29/66545
摘要： A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A silicide metal is then deposited and reacted with the underlying silicon to form a salicide over the source and drain regions. A second dielectric layer is then formed on top of the salicide and is formed to be selective relative to the nitride layer. Thereafter, the nitride layer is removed and a final gate dielectric is then formed. Finally, a metal gate conductor is formed on top of the gate dielectric. The metal gate conductor is formed only after all annealing steps are performed to prevent the metal from spiking through the gate dielectric thereby ruining the device.
摘要翻译：形成晶体管的方法包括在刚刚形成衬底上的隔离和有源区域之后的初始处理阶段中形成源极/漏极注入。在介电层顶部的衬底的表面上形成均匀的氮化物层。然后沉积硅化物金属并与下面的硅反应以在源区和漏区上形成自对准硅化物。然后在硅化物的顶部上形成第二电介质层，并且形成为相对于氮化物层是选择性的。此后，去除氮化物层，然后形成最终的栅极电介质。最后，在栅极电介质的顶部形成金属栅极导体。仅在执行所有退火步骤之后才形成金属栅极导体，以防止金属通过栅极电介质尖峰，从而破坏器件。

4. 发明授权

US06239476B1 Integrated circuit isolation structure employing a protective layer and method for making same 有权
标题翻译：采用保护层的集成电路隔离结构及其制造方法
公开(公告)号：US06239476B1
公开(公告)日：2001-05-29
申请号：US09176132
申请日：1998-10-21
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , H. Jim Fulford, Jr.
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A trench surface boundary is defined where the trench sidewalls intersect the upper surface of the semiconductor substrate. The trench may be filled with a trench fill material. A protective layer is then formed above the trench. The protective layer covers the trench and laterally extends above the semiconductor substrate at least a first distance beyond the trench surface boundaries.
摘要翻译：提出了一种用于制造集成电路的方法，其中在半导体衬底的场区域中对沟槽进行构图。沟槽通过沟槽底板和沟槽侧壁限定在半导体衬底的内部。限定沟槽表面边界，其中沟槽侧壁与半导体衬底的上表面相交。沟槽可以填充沟槽填充材料。然后在沟槽上方形成保护层。保护层覆盖沟槽并横向延伸超过沟槽表面边界至少第一距离半导体衬底上方。

5. 发明授权

US5933747A Method and structure for an advanced isolation spacer shell 失效
标题翻译：高级隔离隔离壳的方法和结构
公开(公告)号：US5933747A
公开(公告)日：1999-08-03
申请号：US993390
申请日：1997-12-18
申请人： Mark I. Gardner , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Thomas E. Spikes, Jr.
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method and structure are provided for a spacer shell structure which is formed of dielectric materials seletive to one another. The dielectric materials can be configured into a chosen geometric arrangement. The isolation properties of the spacer shell can be scaled to meet a given set of isolation requirements as determined by the size and density of the IGFET devices being isolated. The method to fabricate the novel spacer shell maintains costly fabrication steps at a minimum. The isolation ability of the novel spacer shell preserves the operation integrity of neighboring IGFET devices. Electrical shorts between adjacent devices are prevented. Capacitive coupling between neighboring IGFET structures is likewise minimized.
摘要翻译：提供了一种隔离壳结构的方法和结构，该隔离壳结构由彼此相互连接的电介质材料形成。介电材料可以被配置成所选择的几何布置。间隔壳的隔离性能可以缩放以满足由隔离的IGFET器件的尺寸和密度所确定的给定的隔离要求。制造新型间隔壳的方法至少保持了昂贵的制造步骤。新型间隔壳的隔离能力保持了相邻IGFET器件的操作完整性。防止相邻设备之间的电气短路。相邻IGFET结构之间的电容耦合同样被最小化。

6. 发明授权

US06599174B1 Eliminating dishing non-uniformity of a process layer 有权
标题翻译：消除处理层的不均匀性
公开(公告)号：US06599174B1
公开(公告)日：2003-07-29
申请号：US09843996
申请日：2001-04-27
申请人： Thomas E. Spikes, Jr.
发明人： Thomas E. Spikes, Jr.
IPC分类号： B24D100
CPC分类号： B24B37/042 , B24B49/04 , H01L21/31053 , H01L22/26
摘要： A method includes providing at least one wafer having a process layer formed thereon. A surface of the process layer is polished using a first polishing process that is comprised of a slurry and a first polishing pad. The slurry is removed from the surface of the process layer. The surface of the process layer is planarized using a substantially slurryless second polishing process that is comprised of a second polishing pad that is more abrasive than the first polishing pad. A system includes a polishing tool and a process controller. The polishing tool is adapted to receive at least one wafer having a process layer formed thereon. The polishing tool is a adapted to polish a surface of the process layer using a first polishing process that is comprised of a slurry and a first polishing pad and remove the slurry from the surface of the process layer. The polishing tool is adapted to planarize the surface of the process layer using a substantially slurryless second polishing process that is comprised of a second polishing pad that is more abrasive than the first polishing pad. The process controller is coupled to the polishing tool and is adapted to communicate with at least one of a slurry controller and the polishing tool.
摘要翻译：一种方法包括提供至少一个其上形成有工艺层的晶片。使用由浆料和第一抛光垫组成的第一抛光工艺来抛光工艺层的表面。从处理层的表面除去浆料。使用基本上无淤泥的第二抛光工艺来平坦化处理层的表面，该抛光工艺包括比第一抛光垫更具磨蚀性的第二抛光垫。系统包括抛光工具和过程控制器。抛光工具适于接纳至少一个具有在其上形成工艺层的晶片。抛光工具适于使用由浆料和第一抛光垫组成的第一抛光工艺来抛光工艺层的表面，并从处理层的表面去除浆料。抛光工具适于使用基本上无淤泥的第二抛光工艺来平坦化工艺层的表面，该抛光工艺包括比第一抛光垫更具磨蚀性的第二抛光垫。过程控制器耦合到抛光工具，并且适于与浆料控制器和抛光工具中的至少一个连通。

7. 发明授权

US06555396B1 Method and apparatus for enhancing endpoint detection of a via etch 有权
标题翻译：用于增强通孔蚀刻的端点检测的方法和装置
公开(公告)号：US06555396B1
公开(公告)日：2003-04-29
申请号：US10097159
申请日：2002-03-13
申请人： Ailian Zhao , John A. Iacoponi , Thomas E. Spikes, Jr.
发明人： Ailian Zhao , John A. Iacoponi , Thomas E. Spikes, Jr.
IPC分类号： H01L2100
CPC分类号： H01L21/31116
摘要： A method is provided to enhance endpoint detection during via etching in the processing of a semiconductor wafer. The method includes forming a first process layer and a second process layer above the first process layer. A first masking layer is formed above at least a portion of the second process layer, leaving an outer edge portion of at least the second process layer exposed. Thereafter, an etching process is used to remove the outer edge portion of the first and second layers. Once the etching is complete, the first masking layer is removed, and a second masking layer is formed above the second process layer. The second masking layer is patterned to expose portions of the first process layer, and then an etching process substantially removes the exposed portions of the first process layer to form the vias.
摘要翻译：提供了一种在半导体晶片的处理中增强通孔蚀刻期间的端点检测的方法。该方法包括在第一处理层上形成第一处理层和第二处理层。第一掩模层形成在第二工艺层的至少一部分之上，留下至少第二工艺层的外边缘部分露出。此后，使用蚀刻工艺去除第一和第二层的外边缘部分。蚀刻完成后，去除第一掩模层，并在第二工艺层上方形成第二掩模层。图案化第二掩模层以暴露第一工艺层的部分，然后蚀刻工艺基本上去除第一工艺层的暴露部分以形成通路。

8. 发明授权

US06225201B1 Ultra short transistor channel length dictated by the width of a sidewall spacer 失效
标题翻译：超短晶体管通道长度由侧壁间隔物的宽度决定
公开(公告)号：US06225201B1
公开(公告)日：2001-05-01
申请号：US09433801
申请日：1999-11-03
申请人： Mark I. Gardner , Derrick J. Wristers , Jon D. Cheek , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Derrick J. Wristers , Jon D. Cheek , Thomas E. Spikes, Jr.
IPC分类号： H01L213205
CPC分类号： H01L29/517 , H01L21/0338 , H01L21/28114 , H01L21/28132 , H01L21/2815 , H01L21/28194 , H01L21/31144 , H01L29/6659 , H01L29/66659 , Y10S438/947
摘要： An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length dictated by the width of a sidewall spacer which either embodies a gate conductor for the transistor or is used to pattern an underlying gate conductor. In one embodiment, the sidewall spacers are formed upon and extending laterally from the opposed sidewall surfaces of a sacrificial material. The sidewall surfaces of the sacrificial material are defined by forming the sacrificial material within an opening interposed laterally between vertically extending sidewalls which bound a gate dielectric. An upper portion of the gate dielectric is removed to partially expose the sidewall surfaces arranged at the periphery of the sacrificial material. Polysilicon spacers are formed exclusively upon the sidewall surfaces of the sacrificial material to define a pair of gate conductors having relatively small lateral widths. Portions of the gate dielectric not arranged exclusively beneath the gate conductors may be selectively removed. In another embodiment, sidewall spacers are used to protect select regions of a polysilicon gate material arranged exclusively underneath the spacers from being etched. The sidewall spacers are formed upon and extending laterally from sidewall surfaces arranged at the periphery of an opening which extends through a masking or sacrificial material to an underlying polysilicon gate material. The sidewall spacers are sacrificial in that they are removed from the semiconductor topography after they have served their purpose of masking the underlying polysilicon gate material.
摘要翻译：提供了一种集成电路制造工艺，用于形成具有由侧壁间隔物的宽度所规定的超短沟道长度的晶体管，该侧壁间隔物体现了晶体管的栅极导体或用于对下面的栅极导体进行图案化。在一个实施例中，侧壁间隔件形成在牺牲材料的相对的侧壁表面上并从牺牲材料的相对侧壁表面延伸。牺牲材料的侧壁表面通过在封闭栅极电介质的垂直延伸侧壁之间横向插入的开口内形成牺牲材料来限定。去除栅极电介质的上部以部分地暴露设置在牺牲材料的周边处的侧壁表面。专门在牺牲材料的侧壁表面上形成多晶硅间隔物，以限定具有相对小的横向宽度的一对栅极导体。可以选择性地去除不排列在栅极导体下方的栅极电介质的部分。在另一个实施例中，侧壁间隔件用于保护专门在间隔物下方布置的多晶硅栅极材料的选择区域被蚀刻。侧壁间隔件形成在侧壁表面上并且从侧壁表面延伸出来，该侧壁表面布置在开口的周边，该开口延伸穿过掩模或牺牲材料到下面的多晶硅栅极材料。侧壁间隔物是牺牲的，因为它们已经用于掩盖下面的多晶硅栅极材料的目的，从半导体拓扑图中去除它们。

9. 发明授权

US6140190A Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors 失效
标题翻译：具有抛光栅电极绝缘栅场效应晶体管的源/漏源升高的方法和结构
公开(公告)号：US6140190A
公开(公告)日：2000-10-31
申请号：US993388
申请日：1997-12-18
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Michael P. Duane
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Michael P. Duane
IPC分类号： H01L21/336 , H01L29/417 , H01L29/49
CPC分类号： H01L29/6659 , H01L29/41775 , H01L29/41783 , H01L29/495 , H01L29/66545
摘要： A method and structure are provided for an IGFET which has elevated source/drain regions and polished gate electrode. The IGFET provides raised doped polysilicon regions between the source/drain areas and subsequent metallization layers. The doped polysilicon regions are scalable. Integration of elevated source/drain regions provides a shallow junction for high performance IGFET design. A refractory metal gate is provided without sacrificing the fabrication advantage of self-aligned techniques. A method to produce an IGFET which incorporates both of the above advantages into a single device, with relatively few process steps, is also provided. Fabricating the gate electrode in this manner will enable metal gate electrodes to be integrated with source/drain structure.
摘要翻译：为具有升高的源极/漏极区域和抛光的栅电极的IGFET提供了一种方法和结构。 IGFET在源极/漏极区域和随后的金属化层之间提供凸起的掺杂多晶硅区域。掺杂多晶硅区域是可扩展的。提升的源极/漏极区域的集成提供了用于高性能IGFET设计的浅结。提供难熔金属栅极，而不牺牲自对准技术的制造优点。还提供了一种产生IGFET的方法，其将上述两个优点并入单个装置，并且具有相对较少的工艺步骤。以这种方式制造栅电极将使金属栅电极与源/漏结构集成。

10. 发明授权

US06309936B1 Integrated formation of LDD and non-LDD semiconductor devices 有权
标题翻译： LDD和非LDD半导体器件的集成形成
公开(公告)号：US06309936B1
公开(公告)日：2001-10-30
申请号：US09163965
申请日：1998-09-30
申请人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
IPC分类号： H01L21336
CPC分类号： H01L21/823418 , H01L21/823468
摘要： A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spacer. A first dopant is implanted into the substrate to form a first heavily doped active region adjacent to the spacer and spaced from the first gate electrode and a second heavily doped active region adjacent to the second gate electrode. The spacer is then removed and a second dopant is implanted into the substrate to form a lightly doped active region adjacent to the first gate electrode. In some instances, gate dielectrics for the first and second gate electrodes are formed using different materials and/or having different thicknesses.
摘要翻译：形成半导体器件的方法包括在衬底上形成第一栅电极，然后在第一栅电极的至少一个侧壁上形成间隔物。在形成间隔物之后，在衬底上形成第二栅电极。将第一掺杂剂注入到衬底中以形成与间隔物相邻的第一重掺杂有源区，并与第一栅极间隔开，并与第二栅电极相邻的第二重掺杂有源区。然后去除间隔物，并将第二掺杂剂注入到衬底中以形成与第一栅电极相邻的轻掺杂有源区。在一些情况下，用于第一和第二栅电极的栅极电介质是使用不同的材料和/或具有不同的厚度来形成的。

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