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1. 发明授权

US5151904A Reconfigurable, multi-user Viterbi decoder 失效
公开(公告)号：US5151904A
公开(公告)日：1992-09-29
申请号：US590238
申请日：1990-09-27
申请人： Thomas C. Reiner , Mark J. Lindsey , Krishnanand Kelkar
发明人： Thomas C. Reiner , Mark J. Lindsey , Krishnanand Kelkar
IPC分类号： H03M13/41
CPC分类号： H03M13/6516 , H03M13/41 , H03M13/6569
摘要： A decoding system for decoding a digital data stream that has been convolutionally encoded in accordance with a selected constraint length and selected polynomial codes, which system includes a processor, such as a Viterbi decoder, that is reconfigurable so that it can decode encoded digital data streams for a number of different user channels for which data streams have been convolutionally encoded in accordance with respectively different combinations of selected constraint length and selected polynomial codes. The decoding system includes a Viterbi decoder for processing the encoded data stream in accordance with said selected constraint length and in accordance with said selected polynomial codes to decode the encoded data stream; a RAM for storing data of said selected constraint length and data of said selected polynomial codes in accordance with which said data stream was encoded; and a RAM I/O interface circuit responsive to a user channel identification signal for retrieving said selected constraint length data and said selected polynomial code data from the RAM and configuring the Viterbi decoder in accordance with said selected constraint length and said selected polynomial codes. In order to accommodate concurrent multiple user channels, the RAM stores different sets of combinations of constraint length data and polynomial code data corresponding to different user channels, with said different sets being retrievable from the RAM in response to respectively different user channel identification signals. The polynomial code data and constraint length data in the RAM may be changed from time to time in response to software instructions, as user channel requirements change. The Viterbi decoder processes said encoded data stream over a plurality of decoding cycles and produces intermediate decoding results during different decoding cycles; and the RAM I/O interface circuit stores in the RAM said intermediate decoding results produced for each different user channel during the different decoding cycles.

2. 发明授权

US5467396A Tamper-proof data storage 失效
标题翻译：防篡改数据存储
公开(公告)号：US5467396A
公开(公告)日：1995-11-14
申请号：US144052
申请日：1993-10-27
申请人： Stephen R. Schossow , Thomas C. Reiner
发明人： Stephen R. Schossow , Thomas C. Reiner
IPC分类号： G06F1/00 , G06F21/00 , G06F12/14 , H04L9/22
CPC分类号： G06F21/72 , G06F21/79
摘要： In a data processing system, stored data that is essential to a given data processing operation, such encryptographic key generation, is tamper proof in that if such data is altered, processing of the altered data is inhibited upon retrieval. The system includes a memory for storing a plurality of data bits and in which the storage of one type of the bits is irreversible; a data processor, such as a cryptographic processor, coupled to the memory for retrieving the bits from a first section of the memory and for processing the retrieved bits with other data bits; an authentication unit coupled to the memory for processing the bits stored in the first section of the memory with bits stored in a second section of the memory to provide an indication as to whether or not the bits stored in the first section of the memory have a predetermined relationship to the bits stored in the second section of the memory; and a gate coupled to the data processor and to the authentication unit for inhibiting the data processor from processing the data bits retrieved from the first section of the memory unless the authentication unit indicates that the bits stored in the first section of the memory have the predetermined relationship to the bits stored in the second section of the memory. Since storage of one type of the bits is irreversible, although a pirate can alter the logic state of one type of bit in one section of the memory, he cannot alter the the logic state of the other type of bit in the other of the memory so as restore the predetermined relationship between the bits in the first section of the memory and the bits in the second section of the memory.
摘要翻译：在数据处理系统中，存储的数据对于给定的数据处理操作是必需的，这种加密密钥生成是防篡改的，因为如果这样的数据被改变，则在检索时处理改变的数据被禁止。该系统包括用于存储多个数据位的存储器，并且其中一种类型的位的存储是不可逆的; 耦合到存储器的数据处理器，例如密码处理器，用于从存储器的第一部分检索位，并且用其它数据位处理检索到的位; 认证单元，耦合到存储器，用于处理存储在存储器的第二部分中的位的存储器的第一部分中的位，以提供关于存储在存储器的第一部分中的位是否具有与存储在存储器的第二部分中的位的预定关系; 以及耦合到数据处理器和验证单元的门，用于禁止数据处理器处理从存储器的第一部分检索的数据位，除非认证单元指示存储在存储器的第一部分中的位具有预定的与存储在存储器的第二部分中的位的关系。由于一种类型的比特的存储是不可逆的，尽管盗版者可以改变存储器的一个部分中的一种类型的比特的逻辑状态，但是他不能改变另一种存储器中的另一种类型的比特的逻辑状态以恢复存储器的第一部分中的位与存储器的第二部分中的位之间的预定关系。

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