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1. 发明授权

US5151904A Reconfigurable, multi-user Viterbi decoder 失效
公开(公告)号：US5151904A
公开(公告)日：1992-09-29
申请号：US590238
申请日：1990-09-27
申请人： Thomas C. Reiner , Mark J. Lindsey , Krishnanand Kelkar
发明人： Thomas C. Reiner , Mark J. Lindsey , Krishnanand Kelkar
IPC分类号： H03M13/41
CPC分类号： H03M13/6516 , H03M13/41 , H03M13/6569
摘要： A decoding system for decoding a digital data stream that has been convolutionally encoded in accordance with a selected constraint length and selected polynomial codes, which system includes a processor, such as a Viterbi decoder, that is reconfigurable so that it can decode encoded digital data streams for a number of different user channels for which data streams have been convolutionally encoded in accordance with respectively different combinations of selected constraint length and selected polynomial codes. The decoding system includes a Viterbi decoder for processing the encoded data stream in accordance with said selected constraint length and in accordance with said selected polynomial codes to decode the encoded data stream; a RAM for storing data of said selected constraint length and data of said selected polynomial codes in accordance with which said data stream was encoded; and a RAM I/O interface circuit responsive to a user channel identification signal for retrieving said selected constraint length data and said selected polynomial code data from the RAM and configuring the Viterbi decoder in accordance with said selected constraint length and said selected polynomial codes. In order to accommodate concurrent multiple user channels, the RAM stores different sets of combinations of constraint length data and polynomial code data corresponding to different user channels, with said different sets being retrievable from the RAM in response to respectively different user channel identification signals. The polynomial code data and constraint length data in the RAM may be changed from time to time in response to software instructions, as user channel requirements change. The Viterbi decoder processes said encoded data stream over a plurality of decoding cycles and produces intermediate decoding results during different decoding cycles; and the RAM I/O interface circuit stores in the RAM said intermediate decoding results produced for each different user channel during the different decoding cycles.

2. 发明授权

US5014310A Video scrambling and descrambling by varying sequence of segments in adjacent video information lines 失效
标题翻译：通过在相邻视频信息行中改变段的序列来对视频进行加扰和解扰
公开(公告)号：US5014310A
公开(公告)日：1991-05-07
申请号：US455554
申请日：1989-12-18
申请人： Gordon K. Walker , William A. Shumate , Krishnanand Kelkar
发明人： Gordon K. Walker , William A. Shumate , Krishnanand Kelkar
IPC分类号： H04N7/169
CPC分类号： H04N7/1696
摘要： A video scrambling system scrambles adjacent sequentially odd and even video information lines of a video frame by simultaneously storing in a memory a pair of such adjacent lines; and forming a pair of scrambled video information lines by retrieving from the memory a segment of one of the stored video information lines followed by a segment of the other stored video information line, and by shifting the phase of one of the retrieved segments of the scrambled video information line in relation to the other retrieved segment of said scrambled video information line by an odd multiple of one-half the phase of the chrominance information cycle. This phase shift causes the phase relationship of all segments with respect to the color reference signal to be the same; and as a result there is no differential hue shift in the descrambled signal. In a complementary descrambling system, the two retrieved segments of each descrambled video information line are retrieved consecutively without an intervening phase shift. Security of the scrambled signal against unauthorized descrambling is enhanced by delaying the provision of an encryption keystream to a control unit that sets the cutpoint between the segments in accordance with said keystream, and further using the keystream to set the amount of said delay.
摘要翻译：视频加扰系统通过在存储器中同时存储一对这样的相邻行来扰乱视频帧的相邻顺序的奇数和偶数视频信息行; 以及通过从所述存储器中检索所存储的视频信息行之一的片段之后的另一个存储的视频信息行的片段，并且通过将加扰的视频信息线中的一个被检索的段的相位移位视频信息线相对于所述加扰视频信息行的另一个检索的段乘以色度信息周期的相位的一半的奇数倍。该相移导致所有段相对于颜色参考信号的相位关系相同; 结果在解扰信号中没有差分色调偏移。在互补解扰系统中，每个解扰视频信息线的两个检索到的段被连续检索，而没有中间的相移。通过将提供加密密钥流延迟到根据所述密钥流在段之间设置切点的控制单元，并进一步使用密钥流来设置所述延迟的量来增强针对未经授权的解扰的加扰信号的安全性。

3. 发明授权

US4879720A Decoder ring system 失效
标题翻译：解码器环系统
公开(公告)号：US4879720A
公开(公告)日：1989-11-07
申请号：US166187
申请日：1988-03-10
申请人： William A. Shumate , Daniel R. Kindred , Franklin P. Antonio , Steven H. Gardner , Krishnanand Kelkar , Thomas R. Bilotta , Steven L. Rogers
发明人： William A. Shumate , Daniel R. Kindred , Franklin P. Antonio , Steven H. Gardner , Krishnanand Kelkar , Thomas R. Bilotta , Steven L. Rogers
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41
CPC分类号： H03M13/41
摘要： A decoding system capable of outputting Viterbi-decoding-algorithm-decoded data at a predetermined rate that is greater than a given rate at which coded data is processed in accordance with said algorithm to produce the decoded data. The system includes a data input bus; a data output bus; a ring of decoders, with each decoder being coupled to the input bus for receiving coded data from the input bus and coupled to the output bus for providing decoded data onto the output bus. Each of the decoders in the ring includes an input buffer, timing controller, decoding processor and output buffer. The input buffer responds to a start-input signal from a preceding decoder in the ring by buffering a block of the received coded data. The timing contoller provides a start-input signal to a succeeding decoder in the ring at such time as to cause the succeeding decoder to receive a block of coded data from the input bus that overlaps the block of coded data received from the input bus by the instant said decoder. The decoding processor processes the buffered block of coded data at a given rate to produce decoded data. The output buffer buffers the block of decoded data. The timing controller also responds to a start-up signal provided by a preceding decoder in the ring by causing the buffered decoded data to be provided onto the data output bus at a predetermined rate that is greater than the given rate at which the coded data is processed to produce the decoded data; and further provides a start-output signal to the succeeding decoder in the ring to cause the succeeding decoder to provide a portion of the buffered decoded data therein onto the data output bus at a predetermined rate and at such time as to be continuous from and not overlap the portion of the buffered decoded provided onto the output data bus from the instant said decoder.
摘要翻译：一种解码系统，能够按照所述算法，按照规定的速度输出维特比解码算法解码数据，该预定速率大于处理编码数据的给定速率，以产生解码数据。该系统包括数据输入总线; 数据输出总线; 解码器环，每个解码器耦合到输入总线，用于从输入总线接收编码数据，并耦合到输出总线，用于将解码的数据提供到输出总线上。环中的每个解码器包括输入缓冲器，定时控制器，解码处理器和输出缓冲器。输入缓冲器通过缓冲接收到的编码数据的块来响应来自前一解码器的起始输入信号。定时轮廓器在环中向下一个解码器提供起始输入信号，以使得后续的解码器从输入总线接收与从输入总线接收的编码数据的块重叠的编码数据块即时解码器。解码处理器以给定的速率处理缓冲的编码数据块以产生解码的数据。输出缓冲器缓冲解码数据块。定时控制器还通过使缓冲的解码数据以大于编码数据的给定速率的预定速率提供到数据输出总线上来响应由环中之前的解码器提供的启动信号处理以产生解码数据; 并且进一步向环中的后续解码器提供起始 - 输出信号，以使后续解码器以预定速率向数据输出总线提供缓冲的解码数据的一部分，并且在这样的时间从而不是将所提供的缓冲解码的部分从所述解码器的瞬间重叠到输出数据总线上。

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