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1. 发明授权

US4633465A Eye violation detectors 失效
标题翻译：眼睛检测器
公开(公告)号：US4633465A
公开(公告)日：1986-12-30
申请号：US716563
申请日：1985-03-27
申请人： Theodore A. Fitch , Michael L. Steinberger
发明人： Theodore A. Fitch , Michael L. Steinberger
IPC分类号： H04L1/20 , H04L25/06 , G06F11/00 , H04B17/00
CPC分类号： H04L25/067 , H04L1/20
摘要： Eye violation detectors which provide either one of a "graded" or "half-graded" eye violation indicator technique. More particularly, the eye violation detector for practicing the "graded" technique provides an eye violation region in one or more eyes of a multiple eye pattern which is uniformly disposed on either side of the center of each of one or more eyes of the multiple pattern and includes a different amplitude in each of the eye patterns of interest. The eye violation detector for practicing the "half-graded" technique provides an eye violation region in one or more eyes of a multiple eye pattern which is disposed on only one side of the center of each of one or more eyes, except for the center eye of the multiple eye pattern, and includes a different amplitude in each of the eye patterns of interest.
摘要翻译：提供“分级”或“半等级”眼睛违规指标技术之一的眼睛违规检测器。更具体地，用于实施“分级”技术的眼睛违规检测器在多眼图的一个或多个眼睛中提供均匀地设置在多重图案的一个或多个眼睛的每一个的中心的任一侧上的眼睛违规区域并且在感兴趣的每个眼图中包括不同的幅度。用于实施“半分级”技术的眼睛违规检测器在多眼睛图案的一个或多个眼睛中提供眼睛违规区域，其仅设置在一个或多个眼睛的每一个的中心的一侧，除了中心多眼睛图案的眼睛，并且在感兴趣的每个眼睛图案中包括不同的幅度。

2. 发明授权

US5062105A Programmable multiplexing techniques for mapping a capacity domain into a time domain within a frame 失效
标题翻译：将容量域映射到框架内的时域中的可编程多路复用技术
公开(公告)号：US5062105A
公开(公告)日：1991-10-29
申请号：US459929
申请日：1990-01-02
申请人： Richard R. McKnight , Michael L. Steinberger
发明人： Richard R. McKnight , Michael L. Steinberger
IPC分类号： H04J3/04 , H04J3/00 , H04J3/06 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/1629 , H04J2203/0046
摘要： Method and apparatus are disclosed for a programmable multiplexer for converting each of one or more input data signals, with individual data rates, into a second higher data rate signal by mapping contiguously arbitarily assigned Capacity Time Slots (CTSs) in a capacity domain frame to Time Slots in a Time Domain frame (TDTSs) so the TDTSs for each input signal are substantially uniformly spread throughout the TD frame. The programmable multiplexer receives separate input data rate signals which are clock synchronized to the multiplexer clock from separate synchronizers, and maps the capacity domain of the input signals to the time frame format using a 2-step or 3-step digit reverse technique. Both techniques decompose the capacity domain address into predetermined digits from predetermined number bases and then combine the digits to perform a similar computation using the number bases in reverse order. The 3-step technique uses an intermediate step of translating the initially determined values for each the predetermined digits using a bit reversal technique.

3. 发明授权

US06202170B1 Equipment protection system 失效
标题翻译：设备保护系统
公开(公告)号：US06202170B1
公开(公告)日：2001-03-13
申请号：US09121148
申请日：1998-07-23
申请人： Peter B. Busschbach , Michael L. Steinberger
发明人： Peter B. Busschbach , Michael L. Steinberger
IPC分类号： G60F1100
CPC分类号： H04Q1/24 , H04L49/557 , H04M3/18
摘要： A system provides automatic protection switching in case of failure or degradation in a function. For example, a system node may have a working server function, a protection server function, one or more client functions, and a control function. In its baseline configuration, the working server function is active, meaning that it is operating on-line with respect to the client functions, while the protection server function is standby, meaning that it is either inactive (i.e., cold standby) or operating off-line with respect to the client functions (i.e., hot standby). The control function monitors the operations of the working server function, and, if a failure or degradation is detected, or if an externally generated switch command is received, the control function will (1) instruct the working server function to change its status from active to standby and (2) instruct the protection server function to change its status from standby to active. In addition, the control function instructs each server function about a protection switch override condition. Each server function communicates its active/standby status as well as the override condition to the client functions (e.g., using in-band signaling). In addition to monitoring the active/standby status and the override condition transmitted from each server function, each client function also performs its own independent monitoring of the status of the server functions to detect failures or other degradation in the server functions. Each client function then applies a specific set of rules to this information to determine which server function to select for its operations. The set of rules are designed to handle race conditions and other ambiguous states.
摘要翻译：系统在功能故障或退化的情况下提供自动保护切换。例如，系统节点可以具有工作服务器功能，保护服务器功能，一个或多个客户机功能和控制功能。在其基线配置中，工作服务器功能是活动的，这意味着它在客户端功能上在线运行，而保护服务器功能处于待机状态，这意味着它处于非活动状态（即冷备用）或运行 - 关于客户端功能（即热备份）。控制功能监控工作服务器功能的操作，如果检测到故障或劣化，或者接收到外部生成的开关命令，则控制功能将（1）指示工作服务器功能将其状态从活动状态改变待机，（2）指示保护服务器功能将其状态从待机状态更改为活动状态。此外，控制功能指示每个服务器功能关于保护开关覆盖条件。每个服务器功能将其主动/待机状态以及覆盖条件传达给客户端功能（例如，使用带内信令）。除了监视主动/待机状态和从每个服务器功能发送的覆盖条件之外，每个客户端功能还执行其自身对服务器功能的状态的独立监视，以检测服务器功能中的故障或其他劣化。然后，每个客户端功能都将特定的一组规则应用于此信息，以确定为其操作选择哪个服务器功能。这套规则旨在处理种族条件和其他模糊状态。

4. 发明授权

US5065396A Inverse multiplexer and demultiplexer techniques 失效
标题翻译：反向多路复用器和解复用器技术
公开(公告)号：US5065396A
公开(公告)日：1991-11-12
申请号：US460209
申请日：1990-01-02
申请人： James J. Castellano , John H. Leshchuk , Michael L. Steinberger
发明人： James J. Castellano , John H. Leshchuk , Michael L. Steinberger
IPC分类号： H04J3/06 , H04J3/00 , H04L25/14 , H04Q11/04
CPC分类号： H04L25/14 , H04J2203/0094
摘要： An Inverse Multiplexer is disclosed which first demultiplexes a first data rate input signal into a plurality of second lower data rate subsectional signals, where each subsectional signal is provided with a periodic synchronization marker and includes a data rate which is less than the channel data rate used to transmit that subsectional signal to a remote terminal. Programmable Multiplexers (PMUXs) then operate to each take one or more subsectional signals that are (1) clock synchronized to a PMUX clock, and (2) a rational fraction of the channel data rate, and map contiguously assigned time slots in a capacity domain frame for each subsectional signal to time slots of a time domain frame format using a 2-step or 3-step digit reverse technique. The resultant time domain format has the input subsectional capacity domain time slots substantially uniformly distributed over the time domain frame. At the receiving end, an Inverse Demultiplexer performs the reverse operation to recover the original first data rate input signal.

5. 发明授权

US07826996B2 Memory-daughter-card-testing apparatus and method 有权
标题翻译：记忆子卡测试仪和方法
公开(公告)号：US07826996B2
公开(公告)日：2010-11-02
申请号：US11679175
申请日：2007-02-26
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G01C31/00 , G06F11/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一个MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

6. 发明授权

US07184916B2 Apparatus and method for testing memory cards 有权
标题翻译：用于测试存储卡的装置和方法
公开(公告)号：US07184916B2
公开(公告)日：2007-02-27
申请号：US10850044
申请日：2004-05-19
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G06F19/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

7. 发明授权

US06381269B1 Test system with signal injection network for characterizing interference and noise tolerance in a digital signal link 有权
标题翻译：具有信号注入网络的测试系统，用于表征数字信号链路中的干扰和噪声容限
公开(公告)号：US06381269B1
公开(公告)日：2002-04-30
申请号：US09322827
申请日：1999-05-28
申请人： David A. Gradl , Michael L. Steinberger
发明人： David A. Gradl , Michael L. Steinberger
IPC分类号： H04B346
CPC分类号： H04B3/46
摘要： A test system for a evaluating a digital signal link includes a data signal generator, a data signal receiver, a digital signal link to be tested and a test interference signal injection (TISI) network connected as part of the digital signal link. The TISI network includes a data signal input port for receiving digital data signals generated by the data signal generator, a data signal output port for providing the digital data signals to the data signal receiver, and a controlled impedance data signal path carrying the digital data signals between the data signal input port and the data signal output port. An interference signal input port receives interference signals over a range of frequencies from an interference signal generator. One or more directional couplers directionally couple the interference signals into the data signal path toward either the data signal output port or the data signal input port at an impedance that substantially matches the impedance of the digital signal link. The directional couplers are configured to maintain d.c. isolation from ground to facilitate the transfer of d.c. coupled data signal logic through the TISI network.
摘要翻译：用于评估数字信号链路的测试系统包括数据信号发生器，数据信号接收器，要测试的数字信号链路和作为数字信号链路的一部分连接的测试干扰信号注入（TISI）网络。 TISI网络包括用于接收由数据信号发生器产生的数字数据信号的数据信号输入端口，用于将数字数据信号提供给数据信号接收器的数据信号输出端口以及承载数字数据信号的受控阻抗数据信号路径数据信号输入端口和数据信号输出端口之间。干扰信号输入端口在干扰信号发生器的频率范围内接收干扰信号。一个或多个定向耦合器以基本上与数字信号链路的阻抗匹配的阻抗将干扰信号定向耦合到数据信号路径中，朝向数据信号输出端口或数据信号输入端口。定向耦合器被配置为保持直流。与地面隔离，方便转运。通过TISI网络耦合数据信号逻辑。

8. 发明授权

US4438530A Adaptive cross-polarization interference cancellation system 失效
标题翻译：自适应交叉极化干扰消除系统
公开(公告)号：US4438530A
公开(公告)日：1984-03-20
申请号：US388032
申请日：1982-06-14
申请人： Michael L. Steinberger
发明人： Michael L. Steinberger
IPC分类号： H04B7/00 , H04B1/10
CPC分类号： H04B7/002
摘要： Separate components of a received signal are transmitted along two distinct paths to the adaptive cross-polarization interference cancellation arrangement. In each path, appropriate circuitry obtains a sample of a desired component in a particular signal, generates a signal representative of the power envelope of the sample, detects the in-phase and quadrature signals of a correlation between the desired component and interference, and generates control signals in response to the correlation signals to provide improved adjustment of the amplitude and phase of the interference in a canceler circuit. Each path includes a single square law device to reduce DC offset in correlation measurements which occur from square law device mismatches.
摘要翻译：接收信号的分离成分沿着两条不同的路径被发送到自适应交叉极化干扰消除装置。在每个路径中，适当的电路在特定信号中获取期望分量的采样，产生代表采样功率包络的信号，检测所需分量与干扰之间相关的同相和正交信号，并产生控制信号以响应于相关信号，以提供对消除器电路中的干扰的幅度和相位的改进的调整。每个路径包括单平方律设备，以减少由平方律设备不匹配发生的相关测量中的DC偏移。

9. 发明授权

US4283795A Adaptive cross-polarization interference cancellation arrangements 失效
标题翻译：自适应交叉极化干扰消除装置
公开(公告)号：US4283795A
公开(公告)日：1981-08-11
申请号：US81366
申请日：1979-10-03
申请人： Michael L. Steinberger
发明人： Michael L. Steinberger
IPC分类号： H04B1/10 , H04B7/00 , H04J11/00
CPC分类号： H04B7/002
摘要： The present invention relates to an adaptive cross-polarization cancellation arrangement where a first desired polarized signal and a second interfering orthogonally polarized signal, including cross-polarization components, are concurrently received at an antenna. In the present arrangement, the orthogonally polarized components of the received signal are separated and transmitted along separate paths and recombined after the phase and amplitude of the separated polarized interfering signal sample has been appropriately adjusted for maximally cancelling cross-polarization components thereof in the other path. A feedback path includes circuitry for obtaining a sample of any remaining interfering signal in the recombined output signal, generating a signal representative of the power envelope of such sample, and then generating appropriate control signals in response to such representative power envelope signal to provide improved adjustment of the amplitude and phase of the separated polarized interfering signal sample.
摘要翻译：本发明涉及自适应交叉偏振消除装置，其中在天线处同时接收包括交叉极化分量的第一期望偏振信号和第二干涉正交极化信号。在本布置中，接收信号的正交极化分量被分离并沿独立路径传输，并且在分离的极化干扰信号样本的相位和幅度已被适当地调整以在其它路径中最大程度地消除交叉极化分量。反馈路径包括用于获得复合输出信号中的任何剩余干扰信号的样本的电路，产生表示这种样本的功率包络的信号，然后响应于这种代表性的功率包络信号产生适当的控制信号以提供改进的调整分离的偏振干涉信号样本的振幅和相位。

10. 发明授权

US08126674B2 Memory-daughter-card-testing method and apparatus 有权
标题翻译：内存 - 子卡测试方法和设备
公开(公告)号：US08126674B2
公开(公告)日：2012-02-28
申请号：US12870516
申请日：2010-08-27
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G01R31/14 , G01R31/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

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