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1. 发明授权

US5157478A Tape automated bonding packaged semiconductor device incorporating a heat sink 失效
标题翻译：带有自动键合封装的半导体器件，包含散热片
公开(公告)号：US5157478A
公开(公告)日：1992-10-20
申请号：US810354
申请日：1991-12-18
申请人： Tetsuya Ueda , Haruo Shimamoto , Yasuhiro Teraoka , Hideya Yagoura , Hiroshi Seki
发明人： Tetsuya Ueda , Haruo Shimamoto , Yasuhiro Teraoka , Hideya Yagoura , Hiroshi Seki
IPC分类号： H01L21/56 , H01L23/16 , H01L23/433 , H01L23/495
CPC分类号： H01L24/50 , H01L21/565 , H01L23/16 , H01L23/4334 , H01L23/49572 , H01L2224/50 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/07802 , H01L2924/16152 , H01L2924/3511
摘要： A packaged semiconductor device includes an insulating film having an opening, a semiconductor chip disposed in the opening of the insulating film and having a plurality of electrodes, a plurality of leads, each having one end connected to a corresponding electrode, the plurality of leads being supported on the insulating film, a heat radiator disposed opposite and spaced from the semiconductor chip, and a resin package body encapsulating the semiconductor chip and part of the heat radiator, leaving a surface of the heat radiator externally exposed and the second ends of the plurality of leads extending outwardly from the package.
摘要翻译：封装半导体器件包括具有开口的绝缘膜，设置在绝缘膜的开口中并具有多个电极的半导体芯片，多个引线，每个引线的一端连接到相应的电极，多个引线为支撑在绝缘膜上，与半导体芯片相对且间隔开的散热器，以及封装半导体芯片和散热器的一部分的树脂封装体，使散热器的外表面露出，并且多个第二端的引线从封装向外延伸。

2. 发明授权

US5064706A Carrier tape including molten resin flow path element for resin packaged semiconductor devices 失效
标题翻译：载带，包括树脂封装半导体器件的熔融树脂流路元件
公开(公告)号：US5064706A
公开(公告)日：1991-11-12
申请号：US281401
申请日：1988-12-08
申请人： Tetsuya Ueda , Haruo Shimamoto , Hideya Yagoura , Hiroshi Seki , Yasuhiro Teraoka
发明人： Tetsuya Ueda , Haruo Shimamoto , Hideya Yagoura , Hiroshi Seki , Yasuhiro Teraoka
IPC分类号： H01L21/60 , H01L21/56 , H01L23/495
CPC分类号： H01L24/50 , H01L21/565 , H01L23/49524 , H01L23/49572 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , Y10S428/901 , Y10S428/906 , Y10T29/49121 , Y10T428/24273 , Y10T428/24298 , Y10T428/24322
摘要： A carrier tape includes a film having an opening for receiving a semiconductor chip to be resin-molded by a pair of mold halves and outer lead holes formed around the periphery of the opening, a plurality of leads for mounting the semiconductor chip on the film, and a resin running portion cooperating, when the mold halves are closed with the film held between the mold halves, with a gate formed on a parting surface of one of the mold halves to define a resin running path which extends from a portion of the film outside the outer lead holes to the opening for guiding a molten resin into the mold halves while preventing the resin from entering the outer lead holes.
摘要翻译：载带包括具有用于接收半导体芯片的开口的膜，该半导体芯片由一对半模形成，并且形成在开口周围的外部引线孔;多个用于将半导体芯片安装在膜上的引线，以及当所述半模被所述半模保持在所述半模之间的所述半模封闭时，与所述半模中的一个的分离面上形成的门形成一个树脂运行路径，从而形成从所述膜的一部分延伸的树脂行进路径，在外部引线孔外面到开口，用于将熔融树脂引导到半模中，同时防止树脂进入外部引线孔。

3. 发明授权

US4839713A Package structure for semiconductor device 失效
标题翻译：半导体器件的封装结构
公开(公告)号：US4839713A
公开(公告)日：1989-06-13
申请号：US156571
申请日：1988-02-17
申请人： Yasuhiro Teraoka , Tetsuya Ueda , Hideya Yagoura , Haruo Shimamoto , Shigeyuki Nango , Toshinobu Banjo , Hiroshi Seki
发明人： Yasuhiro Teraoka , Tetsuya Ueda , Hideya Yagoura , Haruo Shimamoto , Shigeyuki Nango , Toshinobu Banjo , Hiroshi Seki
IPC分类号： H01L23/057 , H01L23/24 , H01L23/31 , H01L23/495
CPC分类号： H01L24/50 , H01L23/057 , H01L23/24 , H01L23/3121 , H01L23/49572 , H01L2924/01005 , H01L2924/01033 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082
摘要： A package structure comprising a metallic cap having a bottom wall to which the bottom surface of the semiconductor chip is electrically and mechanically connected, a side wall extending from said bottom wall and surrounding the semiconductor chip, and a flange extending outwardly from said side wall substantially parallel to said bottom wall, said flange supporting the lead conductors thereon through an electrically insulating material. The electrical connection means is disposed between the metallic cap flange and the lead conductor for establishing an electrical connection therebetween. The electrical connection means may comprise an electrically conductive projection formed on the flange of the metal cap, extending through a notch in the insulating material and electrically connected to the lead conductor. The electrical connection means may be an electrically conductive bonding material filled within a cavity defined by an opening in the flange of the metal cap, a through hole in the insulating material and a connecting pad of the lead conductor.
摘要翻译：一种包装结构，包括具有底壁的金属盖，半导体芯片的底表面电气和机械连接到该底壁，从所述底壁延伸并围绕半导体芯片的侧壁，以及从所述侧壁向外延伸的凸缘，平行于所述底壁，所述凸缘通过电绝缘材料在其上支撑引线导体。电连接装置设置在金属帽凸缘和引线导体之间，用于在它们之间建立电连接。电连接装置可以包括形成在金属帽的凸缘上的导电突起，延伸穿过绝缘材料中的凹口并电连接到引线导体。电连接装置可以是填充在由金属盖的凸缘中的开口，绝缘材料中的通孔和引线导体的连接焊盘限定的空腔内的导电接合材料。

4. 发明授权

US5309021A Semiconductor device having particular power distribution interconnection arrangement 失效
标题翻译：具有特定配电互连装置的半导体装置
公开(公告)号：US5309021A
公开(公告)日：1994-05-03
申请号：US961352
申请日：1992-10-15
申请人： Haruo Shimamoto , Jun Shibata , Toru Tachikawa , Tetsuya Ueda , Hiroshi Seki
发明人： Haruo Shimamoto , Jun Shibata , Toru Tachikawa , Tetsuya Ueda , Hiroshi Seki
IPC分类号： H01L21/60 , H01L23/28 , H01L23/495 , H01L23/50 , H05K1/02 , H05K3/34 , H01L39/02 , H01L23/58 , H01L23/12 , H01L23/48
CPC分类号： H01L23/49527 , H01L23/49517 , H05K3/341 , H01L2224/451 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/30107 , H05K1/0263 , H05K2201/10659 , H05K2201/10689 , H05K3/3426 , Y02P70/613
摘要： A semiconductor device according to the present invention has reduced inductance on a power supply line, a grounding line, and signal lines. In this invention, to reduce the length of the power supply connection and that of the grounding connection, a power supply metal post and a grounding metal post are respectively provided on a power supply lead of a semiconductor chip and grounding lead of the semiconductor chip perpendicular to the leads. The metal posts protrude from the resin encapsulating the chip and are connected to lands or a conductive circuit pattern on a printed circuit board. Furthermore, a planar conductor commonly connecting the power supply or grounding potentials is provided.
摘要翻译：根据本发明的半导体器件具有减小电源线，接地线和信号线上的电感。在本发明中，为了减小电源连接的长度和接地连接的长度，分别在半导体芯片的电源引线和半导体芯片的接地引线垂直地设置电源金属柱和接地金属柱到线索金属柱从封装芯片的树脂突出，并连接到印刷电路板上的焊盘或导电电路图案。此外，提供通常连接电源或接地电位的平面导体。

5. 发明申请

US20120005103A1 METHOD AND APPARATUS FOR CONSTRUCTION SIMULATION 审中-公开
标题翻译：用于构造模拟的方法和装置
公开(公告)号：US20120005103A1
公开(公告)日：2012-01-05
申请号：US13173167
申请日：2011-06-30
申请人： Hiroshi Seki , Takeshi Yokota
发明人： Hiroshi Seki , Takeshi Yokota
IPC分类号： G06Q10/00
CPC分类号： G06Q10/103 , G06F17/5004 , G06F2217/34 , G06Q10/04 , G06Q50/08
摘要： In a construction simulation apparatus: a 3-D already-existing model, installation progress data, and a 3-D new-construction model are recorded in databases; a match determination unit determines similarity in one or more installation positions of one or more of pieces of equipment and piping components between the 3-D already-existing model and the 3-D new-construction model; and a progress selection unit selects, as portions of installation schedule data corresponding to the 3-D new-construction model, portions of the installation progress data corresponding to matching portions of the 3-D already-existing model, on the basis of data indicating a correspondence relationship between the 3-D already-existing model and the installation progress data, where the matching portions of the 3-D already-existing model are extracted by the match determination unit and respectively match the portions of the 3-D new-construction model.
摘要翻译：在建筑模拟装置中：数据库中记录了现有3-D模型，安装进度数据和3-D新建模型; 匹配确定单元确定3-D已经存在的模型和3-D新建模型之间的一个或多个设备和管道组件的一个或多个安装位置的相似性; 并且进度选择单元根据指示的三维数据的数据，选择与3-D新建模型相对应的安装进度数据的部分与安装进度数据的对应于3-D已存在模型的匹配部分的部分 3-D已经存在的模型与安装进度数据之间的对应关系，其中3-D已存在模型的匹配部分由匹配确定单元提取，并且分别匹配3-D新建模型的部分，施工模式。

6. 发明授权

US07969897B2 Relay device, computer readable medium storing test program and a method for testing relay device 失效
标题翻译：中继装置，存储测试程序的计算机可读介质和中继装置的测试方法
公开(公告)号：US07969897B2
公开(公告)日：2011-06-28
申请号：US12323787
申请日：2008-11-26
申请人： Hiroshi Seki , Hiroyuki Kaneda , Masayuki Kanno , Akira Nakamizu , Syuuhei Ueno
发明人： Hiroshi Seki , Hiroyuki Kaneda , Masayuki Kanno , Akira Nakamizu , Syuuhei Ueno
IPC分类号： H04L12/26 , G06F11/00
CPC分类号： H04L49/555 , H04L43/50 , H04L45/02 , H04L49/3009 , H04L49/557
摘要： A relay device for relaying transfer data to be transmitted between the devices has a plurality of testers. Each of the testers determines whether received transfer data is normal or not, and discards the transfer data that is determined abnormal. The relay device also has a counter that counts a number of transfer data discarded by each of the testers respectively, and a determiner that determines whether an operation of each tester is normal or not based on the number of discarded transfer data counted by the counter.
摘要翻译：用于中继要在设备之间传输的传送数据的中继设备具有多个测试器。每个测试者确定接收的传输数据是否正常，并丢弃确定为异常的传输数据。中继装置还具有计数器，其分别对每个测试器分别丢弃的传送数据的数量进行计数;以及确定器，其基于由计数器计数的丢弃的传送数据的数量来确定每个测试仪的操作是否正常。

7. 发明授权

US07577022B2 Electric element, memory device, and semiconductor integrated circuit formed using a state-variable material whose resistance value varies according to an applied pulse voltage 有权
标题翻译：电元件，存储器件和使用状态变量材料形成的半导体集成电路，其电阻值根据施加的脉冲电压而变化
公开(公告)号：US07577022B2
公开(公告)日：2009-08-18
申请号：US11918983
申请日：2005-09-09
申请人： Shunsaku Muraoka , Koichi Osano , Satoru Mitani , Hiroshi Seki
发明人： Shunsaku Muraoka , Koichi Osano , Satoru Mitani , Hiroshi Seki
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/15 , G11C2213/31 , G11C2213/72 , G11C2213/77 , H01L27/101 , H01L27/1021 , H01L27/2463 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： An electric element includes: a first electrode (1); a second electrode (3); and a layer (2) connected between the first electrode and the second electrode and having a diode characteristic and a variable resistance characteristic. The layer (2) conducts a substantial electric current in a forward direction extending from one of the first electrode (1) and the second electrode (3) to the other electrode as compared to a reverse direction opposite of the forward direction. The resistance value of the layer (2) for the forward direction increases or decreases according to a predetermined pulse voltage applied between the first electrode (1) and the second electrode (3).
摘要翻译：电气元件包括：第一电极（1）; 第二电极（3）; 以及连接在第一电极和第二电极之间并具有二极管特性和可变电阻特性的层（2）。与第一电极（1）和第二电极（3）之一延伸的正向方向相比，与正向相反的方向，层（2）传导大量的电流。根据施加在第一电极（1）和第二电极（3）之间的预定脉冲电压，正向的层（2）的电阻值增加或减少。

8. 发明申请

US20090067215A1 Electric element, memory device, and semiconductor integrated circuit 有权
标题翻译：电子元件，存储器件和半导体集成电路
公开(公告)号：US20090067215A1
公开(公告)日：2009-03-12
申请号：US11918983
申请日：2005-09-09
申请人： Shunsaku Muraoka , Koichi Osano , Satoru Mitani , Hiroshi Seki
发明人： Shunsaku Muraoka , Koichi Osano , Satoru Mitani , Hiroshi Seki
IPC分类号： G11C11/00 , G11C7/00 , G11C8/08 , H01L47/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/15 , G11C2213/31 , G11C2213/72 , G11C2213/77 , H01L27/101 , H01L27/1021 , H01L27/2463 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： An electric element comprises: a first electrode (1); a second electrode (3); and a layer (2) connected between the first electrode and the second electrode and having a diode characteristic and a variable resistance characteristic. The layer (2) conducts a substantial electric current in a forward direction extending from one of the first electrode (1) and the second electrode (3) to the other electrode as compared to a reverse direction opposite of the forward direction. The resistance value of the layer (2) for the forward direction increases or decreases according to a predetermined pulse voltage applied between the first electrode (1) and the second electrode (3).
摘要翻译：电元件包括：第一电极（1）; 第二电极（3）; 以及连接在第一电极和第二电极之间并具有二极管特性和可变电阻特性的层（2）。与第一电极（1）和第二电极（3）之一延伸的正向方向相比，与正向相反的方向，层（2）传导大量的电流。根据施加在第一电极（1）和第二电极（3）之间的预定脉冲电压，正向的层（2）的电阻值增加或减少。

9. 发明授权

US07350855B2 Vehicle water drainage structure 有权
标题翻译：车辆排水结构
公开(公告)号：US07350855B2
公开(公告)日：2008-04-01
申请号：US11480550
申请日：2006-07-05
申请人： Hiroshi Seki
发明人： Hiroshi Seki
IPC分类号： B60R27/00
CPC分类号： B60H1/3233
摘要： A water drainage structure is provided to prevent drainage water from getting on hot components inside the engine compartment and suppress the occurrence of evaporation noise. At least one water drainage opening is provided in a bottom portion of a vehicle member arranged on the under surface of a floor panel of a vehicle. The downstream end portion of a water drainage pipe is arranged to communicate with the inside of a closed cross sectional structure formed by the floor panel and the vehicle member. Drainage water from a vehicle device flows out of the downstream end portion of the water drainage pipe and is discharged to the outside of the vehicle through the water drainage openings of the vehicle member. As a result, the drainage water is prevented from getting on hot components inside the engine compartment of the vehicle and the occurrence of evaporation noise is suppressed.
摘要翻译：提供排水结构，以防止排水从发动机舱内的热部件上排出，并抑制蒸发噪音的发生。至少一个排水口设置在布置在车辆底板的下表面上的车辆构件的底部中。排水管的下游端部布置成与由地板镶板和车辆构件形成的封闭横截面结构的内部连通。来自车辆装置的排水从排水管的下游端部流出，通过车辆部件的排水口排出到车辆外部。结果，能够防止排水在车内的发动机室内发热，能够抑制蒸发噪音的发生。

10. 发明授权

US07191421B2 Integrated circuit design apparatus, method and program evaluating condition of functional blocks, assigned to virtual placement regions in each of lower-and higher-rank mounting blocks 有权
标题翻译：功能块的集成电路设计装置，方法和程序评估条件，分配给每个下级和更高级安装块中的虚拟放置区域
公开(公告)号：US07191421B2
公开(公告)日：2007-03-13
申请号：US10103895
申请日：2002-03-25
申请人： Yasuo Amano , Hiroshi Seki , Yukio Makino , Yumiko Yamanishi , Yoshiko Nakanishi , Yoichiro Ishikawa
发明人： Yasuo Amano , Hiroshi Seki , Yukio Makino , Yumiko Yamanishi , Yoshiko Nakanishi , Yoichiro Ishikawa
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5072
摘要： An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.
摘要翻译：集成电路设计装置包括块放置处理单元，其执行在较高等级的安装块中创建较低等级的安装块的处理，并且执行在下级安装块中的每一个中创建虚拟放置区域的处理，以及高级安装座。功能块分配处理单元对由块放置处理单元提供的每个虚拟放置区域执行功能块的分配处理。评估处理单元提供分配给下级安装块和高级安装块的每个虚拟放置区域的功能块的状态的显示，以便评估所分配的功能块的状况。

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