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1. 发明申请

US20060154417A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20060154417A1
公开(公告)日：2006-07-13
申请号：US11330806
申请日：2006-01-11
申请人： Naoyuki Shinmura , Shigeo Ohnishi , Tetsuya Ohnishi , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri
发明人： Naoyuki Shinmura , Shigeo Ohnishi , Tetsuya Ohnishi , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri
IPC分类号： H01L21/8242
CPC分类号： H01L45/1675 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641
摘要： The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower electrode lines and insulating layers provided on both sides of the lower electrode line so as to be substantially uniform in the height thus for patterning the lower electrode lines, a memory element layer depositing step of depositing on the lower electrode lines a memory element layer for the memory elements, and an annealing step of annealing with heat treatment either between the lower electrode lines forming step and the memory element layer depositing step or after the memory element layer depositing step so that any damages caused by the polishing of the surface of the lower electrode lines can be eliminated.
摘要翻译：本发明涉及一种制造半导体存储器件的方法，该半导体存储器件被布置成具有设置在上部和下部电极之间的存储元件的交叉点存储器阵列，用于存储数据。本发明包括下电极线，其形成步骤：将设置在下电极线两侧的每个下电极线和绝缘层平坦化，以使其高度大致均匀，从而构图下电极线;存储元件在下电极线上沉积用于存储元件的存储元件层的层沉积步骤，以及在下电极线形成步骤和存储元件层沉积步骤之间或在存储元件层沉积之后进行热处理退火的退火步骤使得可以消除由下电极线的表面的抛光引起的任何损坏。

2. 发明申请

US20110089395A1 STRUCTURE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件的结构和制造方法
公开(公告)号：US20110089395A1
公开(公告)日：2011-04-21
申请号：US12976113
申请日：2010-12-22
申请人： Tetsuya OHNISHI , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya OHNISHI , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
摘要翻译：具有交叉点结构的半导体存储器件包括沿一个方向延伸的多个上电极和布置成沿与上电极的一个方向成直角的另一方向延伸的多个下电极。记录材料设置在上电极和下电极之间用于存储数据。记忆材料由钙钛矿材料制成，并且布置在沿着相应的上电极延伸的相应上电极的下电极侧。

3. 发明申请

US20060102943A1 Structure and manufacturing method of semiconductor memory device 有权
标题翻译：半导体存储器件的结构和制造方法
公开(公告)号：US20060102943A1
公开(公告)日：2006-05-18
申请号：US11274258
申请日：2005-11-16
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L29/94
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
摘要翻译：具有交叉点结构的半导体存储器件包括沿一个方向延伸的多个上电极和布置成沿与上电极的一个方向成直角的另一方向延伸的多个下电极。记录材料设置在上电极和下电极之间用于存储数据。记忆材料由钙钛矿材料制成，并且布置在沿着相应的上电极延伸的相应上电极的下电极侧。

4. 发明授权

US08030695B2 Structure and manufacturing method of semiconductor memory device 有权
公开(公告)号：US08030695B2
公开(公告)日：2011-10-04
申请号：US12976113
申请日：2010-12-22
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L21/02
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

5. 发明授权

US07879626B2 Structure and manufacturing method of semiconductor memory device 有权
标题翻译：半导体存储器件的结构和制造方法
公开(公告)号：US07879626B2
公开(公告)日：2011-02-01
申请号：US11274258
申请日：2005-11-16
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
摘要翻译：具有交叉点结构的半导体存储器件包括沿一个方向延伸的多个上电极和布置成沿与上电极的一个方向成直角的另一方向延伸的多个下电极。记录材料设置在上电极和下电极之间用于存储数据。记忆材料由钙钛矿材料制成，并且布置在沿着相应的上电极延伸的相应上电极的下电极侧。

6. 发明申请

US20120219675A1 APPARATUS AND METHOD FOR MANUFACTURING PET FOOD 有权
标题翻译：制造PET食品的装置和方法
公开(公告)号：US20120219675A1
公开(公告)日：2012-08-30
申请号：US13368183
申请日：2012-02-07
申请人： Yoshiharu Okamoto , Masayuki Tajiri
发明人： Yoshiharu Okamoto , Masayuki Tajiri
IPC分类号： A23P1/12 , A23P1/08 , A23L3/40 , H05B6/64 , A23K1/00
CPC分类号： A23N17/004 , A23K40/20 , A23K40/25 , A23K50/40 , A23N17/005
摘要： A manufacturing apparatus and a manufacturing method of pet food are provided. The manufacturing apparatus comprises a material inlet through which a kneaded material is fed, the kneaded material being obtained through kneading a raw pet food material; an extrusion molding section configured to extrude the kneaded material through an extruding outlet; a cutter configured to cut the kneaded material extruded through the extruding outlet at desired intervals to form material grains; a reservoir disposed in a location to receive the material grains falling due to the cutting; an agitating section provided in the reservoir and configured to agitate the material grains; a heating section configured to heat the material grains while the material grains are agitated by the agitating section; and a drying section configured to dry the material grains within the reservoir after the heating.
摘要翻译：提供宠物食品的制造装置和制造方法。该制造装置包括通过捏合原料的宠物食材得到的捏合材料的材料入口，挤出成形部，其构造成通过挤压出口挤出混炼物; 切割器，其被构造成以期望的间隔切割通过挤出出口挤出的捏合材料以形成材料颗粒; 设置在容纳由于切割而落下的材料颗粒的位置的储存器; 搅拌部，设置在所述储存器中并且构造成搅拌所述材料颗粒; 加热部，其构造成在所述搅拌部搅拌所述材料粒子的同时加热所述材料粒子; 以及干燥部，其被配置为在加热之后干燥储存器内的材料颗粒。

7. 发明申请

US20060099724A1 Memory cell with buffered layer 有权
标题翻译：带缓冲层的存储单元
公开(公告)号：US20060099724A1
公开(公告)日：2006-05-11
申请号：US11314222
申请日：2005-12-21
申请人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
发明人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

8. 发明申请

US20050054119A1 Buffered-layer memory cell 失效
标题翻译：缓冲层存储单元
公开(公告)号：US20050054119A1
公开(公告)日：2005-03-10
申请号：US10755654
申请日：2004-01-12
申请人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
发明人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
IPC分类号： H01L27/10 , G11C13/00 , H01L27/24 , H01L45/00 , H01L21/00 , G11C11/00 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的某些方面，半导体缓冲层由厚度在10至200纳米（nm）范围内的YBa2Cu3O7-X（YBCO），氧化铟（In2O3）或氧化钌（RuO2）形成。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr1-XCaXMnO3（PCMO）记忆膜，其中x在0.1和0.6之间的区域中，厚度在10至200nm的范围内。

9. 发明申请

US20140084346A1 SWITCHING ELEMENT 有权
标题翻译：开关元件
公开(公告)号：US20140084346A1
公开(公告)日：2014-03-27
申请号：US14119934
申请日：2012-04-02
申请人： Masayuki Tajiri
发明人： Masayuki Tajiri
IPC分类号： H01L29/778 , H01L29/20 , H01L29/205
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/205 , H01L29/41725 , H01L29/42316 , H01L29/66462 , H01L29/7787
摘要： Provided is a switching element capable of effectively preventing a collapse phenomenon. A switching element (la) includes an electron running layer (12), an electron supplying layer (13) formed on an upper surface of the electron running layer (12), having a band gap larger than that of the electron running layer (12), and forming a heterojunction with the electron running layer (12), a recombination layer (17) formed on an upper surface of the electron supplying layer (13) and having a band gap smaller than that of the electron supplying layer (13), a source electrode (14) and a drain electrode (15) at least partially formed on the upper surface of the electron running layer (12), and a gate electrode (16) at least partially formed on the upper surface of the electron supplying layer (13) and arranged between the source electrode (14) and the drain electrode (15). When the switching element (la) is in an off state, electrons and holes are recombined in the recombination layer (17).
摘要翻译：提供能够有效地防止塌陷现象的开关元件。开关元件（1a）包括电子运行层（12），形成在电子运行层（12）的上表面上的电子供给层（13），其带隙大于电子运行层（12）的带隙），与电子运行层（12）形成异质结，在电子供给层（13）的上表面上形成并且具有小于电子供给层（13）的带隙的复合层（17），至少部分地形成在电子运行层（12）的上表面上的源电极（14）和漏电极（15），以及至少部分地形成在电子供给层的上表面上的栅电极层（13）并且布置在源电极（14）和漏电极（15）之间。当开关元件（1a）处于截止状态时，电子和空穴在复合层（17）中再结合。

10. 发明授权

US07397688B2 Nonvolatile variable resistor, memory device, and scaling method of nonvolatile variable resistor 有权
标题翻译：非易失性可变电阻器，存储器件和易失性可变电阻器的定标方法
公开(公告)号：US07397688B2
公开(公告)日：2008-07-08
申请号：US10700467
申请日：2003-11-05
申请人： Masayuki Tajiri
发明人： Masayuki Tajiri
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/72 , G11C2213/79 , H01L27/101 , H01L27/2409 , H01L27/2436 , H01L28/20 , H01L45/04 , H01L45/1226 , H01L45/147
摘要： Provided are a nonvolatile variable resistor with a structure capable of suppressing an increase in resistance in a case where scaling is applied to reduce a projected area on a plane, a memory device using the nonvolatile variable resistor, and a scaling method of a nonvolatile variable resistor. A first electrode and a second electrode formed on a substrate face each other in a direction of a surface of the substrate. The first electrode is used as an inner electrode, a nonvolatile variable resistance body is formed on an outer surface of the first electrode and the second electrode is formed as an outer electrode on an outer surface of the nonvolatile variable resistance body.
摘要翻译：提供了一种非易失性可变电阻器，其具有能够抑制在施加缩放以减小平面上的投影面积的情况下的电阻增加的结构，使用非易失性可变电阻器的存储器件以及非易失性可变电阻器的缩放方法。形成在基板上的第一电极和第二电极在基板表面的方向上彼此面对。第一电极用作内部电极，在第一电极的外表面上形成非易失性可变电阻体，并且在非易失性可变电阻体的外表面上形成第二电极作为外部电极。

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