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1. 发明授权

US08063433B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08063433B2
公开(公告)日：2011-11-22
申请号：US12109340
申请日：2008-04-24
申请人： Tetsuya Ishimaru , Yasuhiro Shimamoto , Toshiyuki Mine , Yasunobu Aoki , Koichi Toba , Kan Yasui
发明人： Tetsuya Ishimaru , Yasuhiro Shimamoto , Toshiyuki Mine , Yasunobu Aoki , Koichi Toba , Kan Yasui
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/42344 , H01L29/513 , H01L29/66833
摘要： A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm−3 or less.
摘要翻译：存储单元包括由作为电荷捕获部分的氮化硅膜SIN和位于氮化硅膜下面的氧化物膜BOTOX和TOPOX的叠层膜，ONO膜上的存储栅电极MG，源区MS和漏区MD，并且通过在存储单元中的热载流子注入来执行编程或擦除。在存储单元中，氮化硅膜SIN中包含的N-H键和Si-H键的总浓度为5×10 20 cm -3以下。

2. 发明申请

US20080265286A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080265286A1
公开(公告)日：2008-10-30
申请号：US12109340
申请日：2008-04-24
申请人： Tetsuya ISHIMARU , Yasuhiro Shimamoto , Toshiyuki Mine , Yasunobu Aoki , Koichi Toba , Kan Yasui
发明人： Tetsuya ISHIMARU , Yasuhiro Shimamoto , Toshiyuki Mine , Yasunobu Aoki , Koichi Toba , Kan Yasui
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/42344 , H01L29/513 , H01L29/66833
摘要： A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm−3 or less.
摘要翻译：存储单元包括由作为电荷捕获部分的氮化硅膜SIN和位于氮化硅膜下面的氧化物膜BOTOX和TOPOX的叠层膜，ONO膜上的存储栅电极MG，源区MS和漏区MD，并且通过在存储单元中的热载流子注入来执行编程或擦除。在存储单元中，氮化硅膜Sin中包含的N-H键和Si-H键的总浓度为5×10 20 -3 -3以下。

3. 发明授权

US08125012B2 Non-volatile memory device with a silicon nitride charge holding film having an excess of silicon 有权
标题翻译：具有氮化硅电荷保持膜的非易失性存储器件具有过量的硅
公开(公告)号：US08125012B2
公开(公告)日：2012-02-28
申请号：US11639134
申请日：2006-12-15
申请人： Toshiyuki Mine , Kan Yasui , Tetsuya Ishimaru , Yasuhiro Shimamoto
发明人： Toshiyuki Mine , Kan Yasui , Tetsuya Ishimaru , Yasuhiro Shimamoto
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L29/42344 , H01L29/512 , H01L29/513 , H01L29/792 , Y10S438/954
摘要： Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.
摘要翻译：通过热电子进行电子写入和通过热孔进行空穴擦除的非易失性半导体存储装置的性能得到改善。通过电子执行写入操作和通过空穴的擦除操作的非易失性存储单元具有设置在Si衬底上的p型阱区域，隔离区域，源极区域和漏极区域。通过栅极绝缘膜在源极区域和漏极区域之间形成控制栅电极。在控制栅电极的左侧壁形成有底部的氧化硅膜，电荷保持膜，顶部氧化物膜和存储栅电极。电荷保持膜由化学计量过度地含有硅的氮化硅膜形成。

4. 发明申请

US20070170495A1 Non-volatile semiconductor storage device and manufacturing method of the same 有权
标题翻译：非挥发性半导体存储器件及其制造方法相同
公开(公告)号：US20070170495A1
公开(公告)日：2007-07-26
申请号：US11639134
申请日：2006-12-15
申请人： Toshiyuki Mine , Kan Yasui , Tetsuya Ishimaru , Yasuhiro Shimamoto
发明人： Toshiyuki Mine , Kan Yasui , Tetsuya Ishimaru , Yasuhiro Shimamoto
IPC分类号： H01L29/792
CPC分类号： H01L29/42344 , H01L29/512 , H01L29/513 , H01L29/792 , Y10S438/954
摘要： Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.
摘要翻译：通过热电子进行电子写入和通过热孔进行空穴擦除的非易失性半导体存储装置的性能得到改善。通过电子执行写入操作和通过空穴的擦除操作的非易失性存储单元具有设置在Si衬底上的p型阱区域，隔离区域，源极区域和漏极区域。通过栅极绝缘膜在源极区域和漏极区域之间形成控制栅电极。在控制栅电极的左侧壁形成有底部的氧化硅膜，电荷保持膜，顶部氧化物膜和存储栅电极。电荷保持膜由化学计量过度地含有硅的氮化硅膜形成。

5. 发明授权

US08796756B2 Nonvolatile semiconductor device and method of manufacturing the same 有权
标题翻译：非易失性半导体器件及其制造方法
公开(公告)号：US08796756B2
公开(公告)日：2014-08-05
申请号：US13755348
申请日：2013-01-31
申请人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasafumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
发明人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasafumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L29/792
摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.
摘要翻译：插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为小于40nm。因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

6. 发明授权

US07915666B2 Nonvolatile semiconductor memory devices with charge injection corner 有权
标题翻译：具有电荷注入角的非易失性半导体存储器件
公开(公告)号：US07915666B2
公开(公告)日：2011-03-29
申请号：US12124143
申请日：2008-05-20
申请人： Kan Yasui , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
发明人： Kan Yasui , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/11526 , H01L27/11546 , H01L29/42344
摘要： An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.
摘要翻译：在存储栅电极上设置有局部集中电场的角部的擦除方法，并且使用Fowler-Nordheim隧道操作将存储栅电极中的电荷注入栅极电介质中的电荷陷阱膜。由于通过Fowler-Nordheim隧道可以减少擦除时的电流消耗，因此可以减少存储器模块的电源电路区域。由于可以提高写入干扰电阻，所以可以通过采用更简单的存储器阵列配置来减少存储器阵列区域。由于这两个效果，可以大大减少存储器模块的面积，从而可以降低制造成本。此外，由于写入和擦除的电荷注入中心彼此一致，所以（编程和擦除）耐久性得到改善。

7. 发明申请

US20130140622A1 NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20130140622A1
公开(公告)日：2013-06-06
申请号：US13755348
申请日：2013-01-31
申请人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasufumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
发明人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasufumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L29/792
摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

8. 发明授权

US08390053B2 Nonvolatile semiconductor device including a field effect transistor having a charge storage layer of predetermined length 失效
标题翻译：包括具有预定长度的电荷存储层的场效应晶体管的非易失性半导体器件
公开(公告)号：US08390053B2
公开(公告)日：2013-03-05
申请号：US12188412
申请日：2008-08-08
申请人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasufumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
发明人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasufumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L29/792
摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.
摘要翻译：插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为小于40nm。因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

9. 发明授权

US08472258B2 Semiconductor nonvolatile memory device 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US08472258B2
公开(公告)日：2013-06-25
申请号：US13269425
申请日：2011-10-07
申请人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

10. 发明授权

US08324092B2 Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate 有权
标题翻译：非易失性半导体器件和制造具有侧壁栅极的嵌入式非易失性半导体存储器件的方法
公开(公告)号：US08324092B2
公开(公告)日：2012-12-04
申请号：US12652517
申请日：2010-01-05
申请人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru , Shin-Ichiro Kimura
发明人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru , Shin-Ichiro Kimura
IPC分类号： H01L21/00
CPC分类号： H01L27/115 , G11C16/0425 , H01L27/11568 , H01L29/42344
摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.
摘要翻译：提供一种制造非挥发性半导体存储器件的方法，其克服了由于最佳栅极高度的差异而引入的离子的渗透问题，同时形成利用侧壁结构的自对准分裂栅型存储单元和缩放MOS晶体管。形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于在逻辑区域的栅电极。栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

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