专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07629827B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07629827B2
公开(公告)日：2009-12-08
申请号：US12167236
申请日：2008-07-02
申请人： Tetsuya Fukuoka , Shigeru Nakahara , Minoru Motoyoshi
发明人： Tetsuya Fukuoka , Shigeru Nakahara , Minoru Motoyoshi
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： The semiconductor integrated circuit includes a first subordinate clock tree 802 and a second subordinate clock tree 803, wherein a clock is delayed by a variable delay circuit 805 and inputted into the second subordinate clock tree 803 so that the phases are matched each other of the output clocks from the end clock drivers with the same position in respective trees, thereby reducing clock skew.
摘要翻译：半导体集成电路包括第一从属时钟树802和第二从属时钟树803，其中，时钟被可变延迟电路805延迟并输入到第二从属时钟树803，使得相位彼此匹配输出来自终端时钟驱动器的时钟在相应树中具有相同的位置，从而减少时钟偏移。

2. 发明申请

US20090072877A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20090072877A1
公开(公告)日：2009-03-19
申请号：US12167236
申请日：2008-07-02
申请人： Tetsuya FUKUOKA , Shigeru Nakahara , Minoru Motoyoshi
发明人： Tetsuya FUKUOKA , Shigeru Nakahara , Minoru Motoyoshi
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： The semiconductor integrated circuit includes a first subordinate clock tree 802 and a second subordinate clock tree 803, wherein a clock is delayed by a variable delay circuit 805 and inputted into the second subordinate clock tree 803 so that the phases are matched each other of the output clocks from the end clock drivers with the same position in respective trees, thereby reducing clock skew.
摘要翻译：半导体集成电路包括第一从属时钟树802和第二从属时钟树803，其中，时钟被可变延迟电路805延迟并输入到第二从属时钟树803，使得相位彼此匹配输出来自终端时钟驱动器的时钟在相应树中具有相同的位置，从而减少时钟偏移。

3. 发明授权

US07612599B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07612599B2
公开(公告)日：2009-11-03
申请号：US12167233
申请日：2008-07-02
申请人： Minoru Motoyoshi , Yasuhiro Fujimura , Shigeru Nakahara
发明人： Minoru Motoyoshi , Yasuhiro Fujimura , Shigeru Nakahara
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.
摘要翻译：可以通过抑制最终级时钟缓冲器和用于提供时钟的时钟分配电路之间的布线引线的波动来减小时钟偏移。考虑到实现时钟偏移的这种减少，时钟分配电路的上游形成为H树结构，并且最终级形成在局部鱼骨结构中。连接到最后级缓冲器的多个主时钟线包括第一主时钟线和第二主时钟线。用于从第一主时钟线接收时钟的多个第一触发器所在的单元布置允许行的数量不同于用于从第一主时钟线接收时钟的多个第一触发器的单元布置允许行数第二主时钟线位于。

4. 发明申请

US20090079488A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090079488A1
公开(公告)日：2009-03-26
申请号：US12167233
申请日：2008-07-02
申请人： Minoru MOTOYOSHI , Yasuhiro Fujimura , Shigeru Nakahara
发明人： Minoru MOTOYOSHI , Yasuhiro Fujimura , Shigeru Nakahara
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.
摘要翻译：可以通过抑制最终级时钟缓冲器和用于提供时钟的时钟分配电路之间的布线引线的波动来减小时钟偏移。考虑到实现时钟偏移的这种减少，时钟分配电路的上游形成为H树结构，并且最终级形成在局部鱼骨结构中。连接到最后级缓冲器的多个主时钟线包括第一主时钟线和第二主时钟线。用于从第一主时钟线接收时钟的多个第一触发器所在的单元布置允许行的数量不同于用于从第一主时钟线接收时钟的多个第一触发器的单元布置允许行数第二主时钟线位于。

5. 发明申请

US20050013160A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050013160A1
公开(公告)日：2005-01-20
申请号：US10917321
申请日：2004-08-13
申请人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
发明人： Keiichi Higeta , Shigeru Nakahara , Hiroaki Nambu
IPC分类号： G11C8/02 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/417 , H01L21/8244 , H01L27/10 , H01L27/11 , G11C11/00
CPC分类号： G11C11/417 , G11C11/412
摘要： Disclosed herein is a semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.
摘要翻译：这里公开了一种半导体存储器件，其具有包括CMOS触发器电路型存储单元的存储器阵列，其能够提高噪声容限，使得读取速度快并降低功耗。在半导体存储器件中，将存储单元的工作电压设定得高于外围电路的工作电压。构成存储单元的MOS晶体管的阈值电压被设定为高于构成外围电路的MOS晶体管的阈值电压。构成存储单元的MOS晶体管的栅极绝缘膜形成为当被转换为相同材料的绝缘膜时，构成构成外围电路的MOS晶体管的栅极绝缘膜更厚。此外，字线选择电平和位线预充电电平被设置为与外围电路的工作电压的电平相同。

6. 发明申请

US20050013159A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050013159A1
公开(公告)日：2005-01-20
申请号：US10917320
申请日：2004-08-13
申请人： Satoshi Iwahashi , Shigeru Nakahara , Takeshi Suzuki , Keiichi Higeta
发明人： Satoshi Iwahashi , Shigeru Nakahara , Takeshi Suzuki , Keiichi Higeta
IPC分类号： G11C11/419 , G11C7/10 , G11C8/16 , G11C11/41 , G11C11/417 , G11C11/00
CPC分类号： G11C7/1069 , G11C7/1051 , G11C8/16 , G11C11/4125
摘要： The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.
摘要翻译：本发明提供了一种新型的半导体集成电路装置，其具有存储电路，高速存储器和大容量存储电路，能够加速和促进定时设定。半导体集成电路器件设有第一放大电路; 其包括第一导电类型的第一MOSFET，其具有为存储单元分别连接的多个位线提供的栅极，并且分别在提供给位线的预充电电压下分别保持在截止状态，作为读取电路存储器单元根据选择字线和存储器信息的操作确定存储器电流是否流动; 并且分别与用于位线的选择信号相关联地进入操作状态，并且还设置有第二放大器电路，其包括：多个第二导电类型的第二MOSFET，其分别具有分别被提供有第一放大器电路的多个放大信号并且以并联配置连接的栅极; 并且其形成对应于第一放大器电路的放大信号的放大信号。

7. 发明授权

US06826109B2 Semiconductor integrated circuit device with a RAM macro having two operation modes for receiving an input signal at different timings 失效
标题翻译：具有RAM宏的半导体集成电路装置具有两种操作模式，用于在不同的定时接收输入信号
公开(公告)号：US06826109B2
公开(公告)日：2004-11-30
申请号：US10345186
申请日：2003-01-16
申请人： Shigeru Nakahara , Satoshi Iwahashi , Takeshi Suzuki , Keiichi Higeta , Kazuo Kanetani
发明人： Shigeru Nakahara , Satoshi Iwahashi , Takeshi Suzuki , Keiichi Higeta , Kazuo Kanetani
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1045 , G11C7/1078 , G11C7/1087 , G11C2207/104
摘要： The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.
摘要翻译：本发明提供了一种半导体集成电路装置，其上安装有能够选择适于提高易用性，易于使用或低功耗或选择输入设定值的操作模式的RAM宏。在RAM宏的第一操作模式中，接收输入信号的定时被设置为第一定时。在第二操作模式中，将接收输入信号的定时设置为晚于第一定时的第二定时。在包括用于接收输入信号的输入电路和用于对输入电路的输出信号进行解码的解码器电路的半导体集成电路装置中，基于第一信号激活输入电路，并且解码器电路基于的第二信号。

8. 发明授权

US06727532B2 Semiconductor integrated circuit device 有权
公开(公告)号：US06727532B2
公开(公告)日：2004-04-27
申请号：US10177044
申请日：2002-06-24
申请人： Takao Saotome , Takeshi Suzuki , Hiroyuki Tanaka , Shigeru Nakahara , Keiichi Higeta
发明人： Takao Saotome , Takeshi Suzuki , Hiroyuki Tanaka , Shigeru Nakahara , Keiichi Higeta
IPC分类号： H01L2710
CPC分类号： G11C5/063 , G11C5/025 , G11C2029/3202
摘要： There is provided a semiconductor integrated circuit device which has realized high speed operation, high integration density and highly efficient layout of the RAM macro, in which a memory array which is divided into four sections in the X and Y coordinates directions is disposed, a first input circuit for receiving a signal which requires optimization for a signal delay is disposed to the center of such four memory arrays, a second input circuit for receiving a data input and control signals thereof is disposed to the center of Y coordinate corresponding to the extending direction of the word line and a signal line for transferring an input signal from the external circuit of the RAM macro to the first and second input circuits is formed using an upper layer wiring for the wiring to form the memory array.

9. 发明授权

US06717877B2 Semiconductor integration circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06717877B2
公开(公告)日：2004-04-06
申请号：US10038663
申请日：2002-01-08
申请人： Takeshi Suzuki , Shigeru Nakahara , Keiichi Higeta , Takeshi Kusunoki
发明人： Takeshi Suzuki , Shigeru Nakahara , Keiichi Higeta , Takeshi Kusunoki
IPC分类号： G11C700
CPC分类号： G11C7/227 , G11C7/22 , G11C11/419 , G11C2207/2254 , G11C2207/2281
摘要： A semiconductor integrated circuit device includes a first variable delay circuit which delays a timing signal for activating a sense amplifier which is supplied with a signal read out from a memory array and amplifies the signal so that a timing difference between a dummy signal read out from a dummy memory cell and the timing signal of the sense amplifier is detected by a detection circuit to be made small in accordance with an output of the detection circuit, and a second variable delay circuit which adjusts a relative timing difference between the dummy signal and the timing signal of the sense amplifier.
摘要翻译：半导体集成电路装置包括：第一可变延迟电路，其延迟用于激活读出放大器的定时信号，读出放大器被提供有从存储器阵列读出的信号，并放大该信号，使得从一个根据检测电路的输出，由检测电路检测出虚拟存储单元和读出放大器的定时信号，使其变小，以及第二可变延迟电路，其调整虚拟信号与定时之间的相对定时差感测放大器的信号。

10. 发明授权

US08086889B2 Semiconductor integrated circuit device for scan testing 有权
标题翻译：半导体集成电路器件进行扫描测试
公开(公告)号：US08086889B2
公开(公告)日：2011-12-27
申请号：US12256535
申请日：2008-10-23
申请人： Yuichi Ito , Yasuhiro Fujimura , Koki Tsutsumida , Shigeru Nakahara
发明人： Yuichi Ito , Yasuhiro Fujimura , Koki Tsutsumida , Shigeru Nakahara
IPC分类号： G06F1/04 , G01R31/28
CPC分类号： G01R31/318552
摘要： A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.
摘要翻译：扫描链组结构，其中为LSI中的每个时钟树系统形成的一组扫描链进行重新连接处理，使得扫描链组不存在于通过对由时钟提供的一个系统的时钟树的区域，并且分配区域中的连接距离变短;测试时钟输入机构，其中要输入到分配区域的测试时钟是独立的子时钟相位;以及开/关机构实现要输入到分配区域的时钟。此外，同时执行的扫描/扫描测试在一个区域或单个区域之间被限制，并且在所有区域中以及在所有区域之间的测试通过多次测试步骤来执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式