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1. 发明授权

US5029121A Digital filter processing device 失效
标题翻译：数字滤波处理装置
公开(公告)号：US5029121A
公开(公告)日：1991-07-02
申请号：US512204
申请日：1990-04-20
申请人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： H03H17/02 , H03H17/06
CPC分类号： H03H17/06
摘要： A digital filter processing device includes at least a plurality of multipliers each for multiplying data signal by coefficient data, and an adder for adding together the multiplication results derived from the multipliers. The digital filter processing device further includes coefficient registers each for storing the coefficient data as is shifted so that a first effective digit of the coefficient data lies at the left end, shift-quantity registers provided in connection with the coefficient registers, and each for storing a quantity of shift equal to the shift quantity of the coefficient data, and barrel shifters each for shifting the digits of an output data from each of the multipliers by the shift quantity stored in each of the shift-quantity registers, in the opposite direction to that of the shift in each of the coefficient registers. The digital filter processing device may further include a second shift-quantity register for storing a second quantity of shift, and a second barrel shifter for shifting the digits of the output data of the adder by the second shift quantity.
摘要翻译：数字滤波处理装置至少包括用于将数据信号乘以系数数据的多个乘法器和用于将从乘法器导出的相乘结果相加的加法器。数字滤波处理装置还包括系数寄存器，每个系数寄存器用于存储被移位的系数数据，使得系数数据的第一有效数字位于左端，与系数寄存器相关联的移位量寄存器，并且每个用于存储移位量等于系数数据的移位量，以及桶形移位器，用于将存储在每个移位量寄存器中的每个移位量寄存器的输出数据的数字移位到与每个移位量寄存器相反的方向上，每个系数寄存器的移位。数字滤波处理装置还可以包括用于存储第二移位量的第二移位量寄存器和用于将加法器的输出数据的数字移位第二移位量的第二桶形移位器。

2. 发明授权

US5027423A Image-processing integrated circuit device 失效
标题翻译：图像处理集成电路器件
公开(公告)号：US5027423A
公开(公告)日：1991-06-25
申请号：US378543
申请日：1989-07-12
申请人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： H04N1/409 , G06T5/20 , H03H17/02
CPC分类号： H03H17/0202
摘要： An image-processing integrated circuit device comprises a delay circuit and adder group, a multiplication block group, and an adder group. Image data in a window are fed to the delay circuit and adder group simultaneously row by row and then added up for every symmetrical positions in the window. The respective sums of the image data thus added up for every symmetrical positions are multiplied by corresponding coefficient data in the multiplication block group. Lastly, the respective results of multiplication obtained from the multiplication block group are added up by the adder group to thereby obtain a filter output. The delay circuit and adder group, the multiplication block group, and the adder group can be integrated to form one image-processing integrated circuit device. Accordingly, the number of parts is reduced. Further, not only the image data can be fed into the delay circuit and adder group simultaneously but also the multiplication in the multiplication block group can be carried out in parallel and simultaneously by using exclusive multiplication blocks each provided for symmetrical positions in the window. Accordingly, the speed in filtering processing becomes high.
摘要翻译：图像处理集成电路装置包括延迟电路和加法器组，乘法块组和加法器组。窗口中的图像数据逐行地馈送到延迟电路和加法器组，然后对于窗口中的每个对称位置相加。对于每个对称位置，这样相加的图像数据的各个和乘以乘法块组中的对应系数数据。最后，由加法器组相加从乘积组获得的相乘乘法结果，从而获得滤波器输出。延迟电路和加法器组，乘法块组和加法器组可以集成形成一个图像处理集成电路器件。因此，部件的数量减少。此外，不仅可以将图像数据同时馈送到延迟电路和加法器组，而且还可以并行地并行地通过使用为窗口中的对称位置提供的专用乘法块来执行乘法器组中的乘法。因此，滤波处理的速度变高。

3. 发明授权

US5778202A Ring bus multiprocessor system and processor boards for constituting the same 失效
标题翻译：环形总线多处理器系统和处理器板构成相同
公开(公告)号：US5778202A
公开(公告)日：1998-07-07
申请号：US662445
申请日：1996-06-10
申请人： Norihiko Kuroishi , Tetsuro Kawata , Kenichi Kawauchi , Nobuaki Miyakawa , Reiji Aibara , Mitsumasa Koyanagi
发明人： Norihiko Kuroishi , Tetsuro Kawata , Kenichi Kawauchi , Nobuaki Miyakawa , Reiji Aibara , Mitsumasa Koyanagi
IPC分类号： G06F15/173 , G06F13/40 , G06F13/00 , G06F13/38
CPC分类号： G06F13/4095
摘要： A ring bus multiprocessor system whose processors are laid out and connected in such a manner that the system is enhanced in stability and performance, is easy to modify in scale, and is lowered in manufacturing cost. On a processor board, processors are serially connected by communication buses to form a processor group. Each processor board may have an even-numbered plurality of processor groups mounted thereon. A plurality of processor boards are laid out in parallel and are interconnected between adjacent boards by means of inter-processor communication buses. Each of the odd-numbered processor groups is connected from one board to the next up to the most downstream board where the connection is looped back to the adjacent even-numbered processor group. In turn, the even-numbered processor group is connected from one board to the next back to the most upstream board where the connection is again looped back to the adjacent odd-numbered processor group, and so on, whereby a ring bus arrangement is formed.
摘要翻译：一种环形总线多处理器系统，其处理器以这样的方式布置和连接，使得系统的稳定性和性能得到提高，容易在规模上进行修改，并降低制造成本。在处理器板上，处理器通过通信总线串联连接，形成处理器组。每个处理器板可以具有安装在其上的偶数个多个处理器组。多个处理器板并联布置并且通过处理器间通信总线在相邻板之间互连。每个奇数处理器组从一个板连接到下一个板到下游板，其中连接被环回到相邻的偶数处理器组。反过来，偶数处理器组从一个板连接到下一个回到最上游板，其中连接再次环回到相邻的奇数处理器组，依此类推，形成环形总线布置。

4. 发明授权

US06219149B1 Print processing apparatus 失效
标题翻译：打印处理装置
公开(公告)号：US06219149B1
公开(公告)日：2001-04-17
申请号：US09050361
申请日：1998-03-31
申请人： Tetsuro Kawata , Yuji Onozawa , Takashi Nagao , Noriaki Seki , Kazutaka Hirata , Yoshinori Wada , Hiroshi Ishikawa
发明人： Tetsuro Kawata , Yuji Onozawa , Takashi Nagao , Noriaki Seki , Kazutaka Hirata , Yoshinori Wada , Hiroshi Ishikawa
IPC分类号： G06F1500
CPC分类号： G06K15/02 , G06K15/1857 , G06K2215/0014 , G06K2215/0062
摘要： A print processing apparatus realizes high speed processing of input data which includes various types of drawing objects such as images, graphics and characters. In the apparatus, input data generated by an input data generating unit is converted into intermediate data in an intermediate data generating element. An intermediate data order controlling element rearranges intermediate data pieces based on overlap therebetween and classifies them into groups, in each of which the data pieces can be processed in parallel. A group ID indicating a group for parallel processing, a hardware configuration ID and so on are assigned to the intermediate data piece. A rasterizing unit receives configuration data from a configuration data administering element, if necessary, in accordance with the hardware configuration ID assigned to the intermediate data piece, and rewrites a function of a reconfigurable rasterizing element under the control of the reconfiguration controlling element. The rasterizing unit rasterizes the intermediate data into dot data and provides it to an outputting unit.
摘要翻译：打印处理装置实现包括各种绘图对象（诸如图像，图形和字符）的输入数据的高速处理。在该设备中，由输入数据生成单元生成的输入数据在中间数据生成元件中被转换为中间数据。中间数据顺序控制元件根据它们之间的重叠重新排列中间数据，并将它们分组成组，其中每个数据段可以并行处理。指示用于并行处理的组的组ID，硬件配置ID等被分配给中间数据块。如果需要，光栅化单元根据分配给中间数据块的硬件配置ID从配置数据管理元件接收配置数据，并且在重配置控制元件的控制下重写可重构光栅化元件的功能。光栅化单元将中间数据光栅化为点数据并将其提供给输出单元。

5. 发明授权

US6100998A Print processor with efficient memory use 失效
标题翻译：打印处理器具有高效的内存使用
公开(公告)号：US6100998A
公开(公告)日：2000-08-08
申请号：US975934
申请日：1997-11-21
申请人： Takashi Nagao , Yuji Onozawa , Hiroshi Ishikawa , Noriaki Seki , Koki Uwatoko , Satoshi Kubota , Koji Adachi , Tetsuro Kawata , Kazutaka Hirata , Yoshinori Wada , Masahiko Koyanagi
发明人： Takashi Nagao , Yuji Onozawa , Hiroshi Ishikawa , Noriaki Seki , Koki Uwatoko , Satoshi Kubota , Koji Adachi , Tetsuro Kawata , Kazutaka Hirata , Yoshinori Wada , Masahiko Koyanagi
IPC分类号： G06K15/02 , G06K15/00
CPC分类号： G06K15/02 , G06K2215/0014 , G06K2215/0065
摘要： A print processor is disclosed which comprises: an input unit for inputting print data including at least either texts or graphics and described in predetermined drawing instructions; an image output unit for outputting images based on data having a predetermined data structure; an intermediate data generating unit for generating intermediate data from the print data, the intermediate data being expressed in a format which is higher in abstract terms than the data structure and which includes at least one basic graphic; an rasterizing process unit for rasterizing the intermediate data into the data structure and for supplying the image output unit with the intermediate data thus rasterized; a determining unit for determining a number and a size of the basic graphics constituting the intermediate data generated by the intermediate data generating unit; an rasterizing time predicting unit for predicting the time it takes the rasterizing process unit to rasterize the intermediate data on the basis of the number and the size of the basic graphics determined by the determining unit; and a control unit for determining an image output speed of the image output unit in accordance with the time predicted by the rasterizing time predicting unit.
摘要翻译：公开了一种打印处理器，其包括：输入单元，用于输入至少包括文本或图形并且在预定绘图指令中描述的打印数据; 图像输出单元，用于基于具有预定数据结构的数据输出图像; 中间数据生成单元，用于从打印数据生成中间数据，中间数据以比数据结构更抽象的方式表示，并且包括至少一个基本图形; 光栅化处理单元，用于将中间数据光栅化为数据结构，并为图像输出单元提供如此光栅化的中间数据; 确定单元，用于确定构成中间数据生成单元生成的中间数据的基本图形的数量和大小; 光栅化时间预测单元，用于基于由所述确定单元确定的所述基本图形的数量和大小预测所述光栅化处理单元所花费的时间来光栅化所述中间数据; 以及控制单元，用于根据由光栅化时间预测单元预测的时间确定图像输出单元的图像输出速度。

6. 发明授权

US06339424B1 Drawing processor 有权
标题翻译：绘图处理器
公开(公告)号：US06339424B1
公开(公告)日：2002-01-15
申请号：US09191541
申请日：1998-11-13
申请人： Hiroshi Ishikawa , Tetsuro Kawata
发明人： Hiroshi Ishikawa , Tetsuro Kawata
IPC分类号： G06F1500
CPC分类号： G06T15/005
摘要： The integrated drawing processor handles the image data that cannot be processed at a required rate by transferring the image data to a non-real-time path unit from an operation processor through an operation processor interface, where the data is processed. Thereafter, the data is transferred through the operation processor interface to the address of a designated storage unit. The transferred data is processed by the operation processor interface necessary, or repeatedly processed by the non-real-time path unit, or transferred to the real-time path unit, and fmally transferred to an output device. The image data that can be processed at the required rate is transferred directly to the real-time path unit through the operation processor interface. The image data transferred to the real-time path unit is outputted to the output device through an output device interface. The drawing processor makes it possible to perform the essential function of the image processing and the auxiliary accelerating function with hardware of a small circuit scale.
摘要翻译：集成绘图处理器通过将处理数据的操作处理器接口从操作处理器传送到非实时路径单元，处理不能以所需速率处理的图像数据。此后，数据通过操作处理器接口传送到指定存储单元的地址。所传输的数据由必要的操作处理器接口处理，或者由非实时路径单元重复处理，或者被传送到实时路径单元，并被传送到输出设备。可以以所需速率处理的图像数据通过操作处理器接口直接传输到实时路径单元。传送到实时路径单元的图像数据通过输出设备接口输出到输出设备。绘图处理器可以用小电路规模的硬件执行图像处理和辅助加速功能的基本功能。

7. 发明授权

US5388193A Symmetrical decoder 失效
标题翻译：对称解码器
公开(公告)号：US5388193A
公开(公告)日：1995-02-07
申请号：US64673
申请日：1993-05-21
申请人： Tetsuro Kawata
发明人： Tetsuro Kawata
IPC分类号： G09G5/20 , G06T11/00 , G09G5/36 , G06F15/62
CPC分类号： G06T11/00
摘要： A decoder used for graphic processing or the like. The decoder includes a first input unit for inputting coordinates of two points, a second input unit for inputting a direction between the two points, and an operation unit for logically operating a relationship between the two points utilizing a symmetry of coordinates on the basis of data supplied from the first and second input units. According to the decoder, the scale of the circuit can be reduced.
摘要翻译：用于图形处理的解码器等。解码器包括用于输入两点坐标的第一输入单元，用于输入两点之间的方向的第二输入单元和用于基于数据利用坐标对称性逻辑运算两点之间的关系的运算单元从第一和第二输入单元提供。根据解码器，电路的规模可以减小。

8. 发明授权

US5274777A Digital data processor executing a conditional instruction within a single machine cycle 失效
标题翻译：数字数据处理器在单个机器周期内执行条件指令
公开(公告)号：US5274777A
公开(公告)日：1993-12-28
申请号：US676692
申请日：1991-03-29
申请人： Tetsuro Kawata
发明人： Tetsuro Kawata
IPC分类号： G06F9/38 , G06F7/24 , G06F9/30 , G06F9/32 , G06F7/36 , G06F7/08
CPC分类号： G06F9/30021 , G06F9/30094
摘要： In a digital data processor having a CPU, a condition instruction is fetched from memory to an instruction register. A first control circuit responds to source-codes to select the general registers having respective pieces of data to be compared. A first latch stores instruction data including a code for an operation to be performed by an arithmetic and logic unit (ALU) on the two pieces of data under the control of a second control circuit. A conditional code register stores a conditional code. representing the result of the ALU operation, and a second latch stores selection criteria for destination registers specified by the instruction. A selection circuit operates under the control of a third control circuit to sort the ALU output data of a third control circuit to the specific destination register in accordance with the selection criteria and the condition code. The instruction execution is completed within a single CPU cycle.
摘要翻译：在具有CPU的数字数据处理器中，条件指令从存储器取出到指令寄存器。第一控制电路响应源代码以选择具有要比较的各个数据段的通用寄存器。在第二控制电路的控制下，第一锁存器存储包括用于由算术和逻辑单元（ALU）执行的操作的代码的指令数据对两条数据的两条数据。条件代码寄存器存储条件代码。代表ALU操作的结果，第二个锁存器存储由该指令指定的目标寄存器的选择标准。选择电路在第三控制电路的控制下工作，以根据选择标准和条件码将第三控制电路的ALU输出数据分类到特定目的地寄存器。指令执行在单个CPU周期内完成。

9. 发明授权

US5448186A Field-programmable gate array 失效
标题翻译：现场可编程门阵列
公开(公告)号：US5448186A
公开(公告)日：1995-09-05
申请号：US214135
申请日：1994-03-16
申请人： Tetsuro Kawata
发明人： Tetsuro Kawata
IPC分类号： G06F7/505 , G06F7/53 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A field-programmable gate array comprises regularly arrayed logic elements, a first group of signal lines interconnecting the logic elements adjacent to each other, and a second group of signal lines interconnecting the logic elements not adjacent to each other to provide a field-programmable gate array capable of forming an adder, logic operation unit, or the like having a high utilization of logic elements.
摘要翻译：现场可编程门阵列包括规则排列的逻辑元件，互连彼此相邻的逻辑元件的第一组信号线和互连不相邻的逻辑元件的第二组信号线，以提供现场可编程门能够形成具有逻辑元件的高利用率的加法器，逻辑运算单元等。

10. 发明授权

US5341309A Apparatus for optimizing hierarchical circuit data base and method for the apparatus 失效
标题翻译：用于优化分级电路数据库和装置的方法的装置
公开(公告)号：US5341309A
公开(公告)日：1994-08-23
申请号：US958714
申请日：1992-10-09
申请人： Tetsuro Kawata
发明人： Tetsuro Kawata
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/5045
摘要： A hierarchical circuit data base optimizing apparatus and a hierarchical circuit data base optimizing method which select and put out a specific partial circuit from a hierarchical circuit data base, compare the number of the interface signals found to be present between this partial circuit and the circuit module at the particular hierarchical level with the number of the interface signals found to be present between this partial circuit and another circuit module at the same hierarchical level, and renews the hierarchical structure of the circuit data base in case the latter number of the interface signals is smaller than the former number.
摘要翻译：分级电路数据库优化装置和分级电路数据库优化方法，从分级电路数据库中选择和放出特定的部分电路，比较发现在该部分电路和电路模块之间的接口信号的数量在特定层次上，发现存在于该部分电路和另一个电路模块之间的接口信号的数量处于相同的层级，并且在后一数量的接口信号为小于前者。

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