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1. 发明授权

US5825314A Variable-length code decoder 失效
标题翻译：可变长度码解码器
公开(公告)号：US5825314A
公开(公告)日：1998-10-20
申请号：US717946
申请日：1996-09-23
申请人： Kenichi Kawauchi , Taro Yokose , Yutaka Koshi , Koumei Tomida , Eiri Hashimoto
发明人： Kenichi Kawauchi , Taro Yokose , Yutaka Koshi , Koumei Tomida , Eiri Hashimoto
IPC分类号： H04N19/00 , H03M7/40 , H03M7/42 , H04N1/41 , H04N19/423 , H04N19/44 , H04N19/91
CPC分类号： H03M7/425
摘要： The present invention provides a variable-length code decoder for inputting a code data bit string having a predetermined number of code data bits in every decoding cycle and decoding it, which comprises storing means for storing a decoded symbol and a node in a code tree in the next decoding cycle corresponding to each combination of a value of the code data bit string and a node in the code tree, reading means for reading the decoded symbol and the node in the code tree in the next decoding cycle from the storing means in accordance with the code data bit string inputted in a current decoding cycle and the node in the code tree in the current decoding cycle, outputting means for outputting the decoded symbol read by the reading means, and providing means for providing the node in the code tree in the next decoding cycle read by the reading means to the reading means.
摘要翻译：本发明提供一种可变长度码解码器，用于在每个解码周期中输入具有预定数量的码数据位的码数据位串，并对其进行解码，该存储装置用于存储解码码元和节点到代码树中对应于码数据位串的值和代码树中的节点的每个组合的下一个解码周期，根据存储装置在下一个解码周期中读取解码符号和代码树中的节点的读取装置在当前解码周期中输入的代码数据位串和当前解码周期中代码树中的节点，输出装置，用于输出由读取装置读取的解码符号;以及提供装置，用于在代码树中提供节点由读取装置读取的下一个解码周期到读取装置。

2. 发明授权

US5596511A Computing method and apparatus for a many-body problem 失效
标题翻译：多体问题的计算方法和装置
公开(公告)号：US5596511A
公开(公告)日：1997-01-21
申请号：US186029
申请日：1994-01-25
申请人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F19/701
摘要： A proximal particle list including numbers of particles located within a predetermined distance from a particular particle is generated in calculating a Coulomb force acting on a particular particle or a related potential. A van der Waals force acting on the particular particle or a related potential is thereafter calculated based on only the particles included in the proximal particle list.
摘要翻译：在计算作用于特定颗粒或相关电位的库仑力时，产生包括位于特定颗粒的预定距离内的颗粒数的近端粒子列表。此后，仅基于近端粒子列表中包含的粒子计算作用于特定粒子或相关电位的范德华力。

3. 发明授权

US5572447A Coordinate difference calculating device 失效
标题翻译：坐标差计算装置
公开(公告)号：US5572447A
公开(公告)日：1996-11-05
申请号：US160800
申请日：1993-12-03
申请人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： G06F7/544 , G06F17/50 , G01N15/02 , G01B21/16
CPC分类号： G06F7/544 , G06F19/704 , G06F19/701
摘要： A device for calculating differences includes a difference circuit for generating difference signals .DELTA.x.sub.j =x.sub.j -x.sub.i, .DELTA.y.sub.j =y.sub.j -y.sub.i, and .DELTA.z.sub.j =z.sub.j -z.sub.i between coordinates of i having (x.sub.i, y.sub.i, z.sub.i) coordinate signals and coordinates of j having (x.sub.j, y.sub.j, z.sub.j) coordinate signals in an orthogonal coordinate system. The difference circuit includes an x-axis circuit, responsive to the x.sub.i and x.sub.j signals having a first circuit for receiving the x.sub.i coordinate signal and the x.sub.j coordinate signal and generating the .DELTA.x.sub.j ; a comparison circuit for comparing the x.sub.i and x.sub.j signals and determining whether the .DELTA.x.sub.j is less than a first set value -L.sub.x /2 corresponding to a length of a side of a virtual rectangular parallelepiped or greater than a second set value L.sub.x /2 corresponding to the length of the side of the virtual rectangular parallelepiped, L.sub.x being a value indicating the length of an elongated side in the x-axis direction of the virtual rectangular parallelepiped; an adder circuit for receiving the L.sub.x and .DELTA.x.sub.j and adding the L.sub.x to .DELTA.x.sub.j when .DELTA.x.sub.j is less than -L.sub.x /2; and a subtraction circuit for receiving the L.sub.x and .DELTA.x.sub.j and subtracting L.sub.x from .DELTA.x.sub.j when .DELTA.x.sub.j is greater than L.sub.x /2. The difference circuit includes y-axis and z-axis circuits similar to the x-axis circuit.
摘要翻译：用于计算差分的装置包括用于产生具有（xi，yi，zi）坐标信号和坐标的坐标之间的差分信号DELTA xj = xj-xi，DELTA yj = yj-yi和DELTA zj = zj-zi的差分电路具有在正交坐标系中的（xj，yj，zj）坐标信号的j。差分电路包括x轴电路，响应于具有用于接收xi坐标信号和xj坐标信号并产生DELTA xj的第一电路的xi和xj信号; 用于比较xi和xj信号并确定DELTA xj是否小于对应于虚拟长方体的一侧的长度或大于第二设定值Lx / 2的对应的第一设定值-Lx / 2的比较电路到虚拟长方体的一侧的长度，Lx是表示虚拟长方体的x轴方向上的细长侧的长度的值; 加法器电路，用于当DELTA xj小于-Lx / 2时，接收Lx和DELTA xj并将Lx加到DELTA xj; 以及减法电路，用于当DELTA xj大于Lx / 2时，从DELTA xj接收Lx和DELTA xj并从DELTA xj中减去Lx。差分电路包括类似于x轴电路的y轴和z轴电路。

4. 发明授权

US5029121A Digital filter processing device 失效
标题翻译：数字滤波处理装置
公开(公告)号：US5029121A
公开(公告)日：1991-07-02
申请号：US512204
申请日：1990-04-20
申请人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： H03H17/02 , H03H17/06
CPC分类号： H03H17/06
摘要： A digital filter processing device includes at least a plurality of multipliers each for multiplying data signal by coefficient data, and an adder for adding together the multiplication results derived from the multipliers. The digital filter processing device further includes coefficient registers each for storing the coefficient data as is shifted so that a first effective digit of the coefficient data lies at the left end, shift-quantity registers provided in connection with the coefficient registers, and each for storing a quantity of shift equal to the shift quantity of the coefficient data, and barrel shifters each for shifting the digits of an output data from each of the multipliers by the shift quantity stored in each of the shift-quantity registers, in the opposite direction to that of the shift in each of the coefficient registers. The digital filter processing device may further include a second shift-quantity register for storing a second quantity of shift, and a second barrel shifter for shifting the digits of the output data of the adder by the second shift quantity.
摘要翻译：数字滤波处理装置至少包括用于将数据信号乘以系数数据的多个乘法器和用于将从乘法器导出的相乘结果相加的加法器。数字滤波处理装置还包括系数寄存器，每个系数寄存器用于存储被移位的系数数据，使得系数数据的第一有效数字位于左端，与系数寄存器相关联的移位量寄存器，并且每个用于存储移位量等于系数数据的移位量，以及桶形移位器，用于将存储在每个移位量寄存器中的每个移位量寄存器的输出数据的数字移位到与每个移位量寄存器相反的方向上，每个系数寄存器的移位。数字滤波处理装置还可以包括用于存储第二移位量的第二移位量寄存器和用于将加法器的输出数据的数字移位第二移位量的第二桶形移位器。

5. 发明授权

US5784012A Variable-length code decoder 失效
标题翻译：可变长度码解码器
公开(公告)号：US5784012A
公开(公告)日：1998-07-21
申请号：US717945
申请日：1996-09-23
申请人： Kenichi Kawauchi , Taro Yokose , Yutaka Koshi , Eiri Hashimoto
发明人： Kenichi Kawauchi , Taro Yokose , Yutaka Koshi , Eiri Hashimoto
IPC分类号： H03M7/40 , H03M7/42
CPC分类号： H03M7/425
摘要： A variable-length code decoder includes plural barrel shifters, each of which executes shift processing on inputted variable-length code data bit by bit from the 0 bit to (the bit number of a maximum length codeword -1). The barrel shifters, which are in number equal to the bit number of the maximum length codeword, are arranged in parallel connection. Plural storing devices are provided, each of which stores a pair of a decoded symbol and codeword length thereof corresponding to code data. Plural fetching devices are provided, each of which fetches the pair of the decoded symbol and the codeword length thereof in accordance with the code data outputted from each of the barrel shifters. Each of the fetching devices is connected to a respective barrel shifter and storing devices. A selecting device is provided for selecting a predetermined pair from plural pairs of the decoded symbol and the codeword length fetched by the plural fetching devices in an initial decoding process. The selecting device further selects any one pair from the plural pairs of the decoded symbol and the codeword length utilizing the codeword length selected in the initial decoding process in subsequent decoding processes.
摘要翻译：可变长度码解码器包括多个桶形移位器，每个桶形移位器对从0位到（最大长度码字-1的位数）逐位执行对输入的可变长度码数据的移位处理。数量等于最大长度码字的位数的桶形移位器被并联布置。提供了多个存储装置，每个存储装置存储对应于代码数据的一对解码符号和码字长度。提供了多个提取装置，每个取出装置根据从每个桶形移位器输出的代码数据，取出一对解码符号及其码字长度。每个取出装置连接到相应的桶形移位器和存储装置。提供了一种选择装置，用于在初始解码处理中从多对解码符号中选择预定的对，以及由多个提取装置获取的码字长度。选择装置利用在后续解码处理中的初始解码处理中选择的码字长度，从多对解码符号和码字长度中进一步选择一对。

6. 发明授权

US5027423A Image-processing integrated circuit device 失效
标题翻译：图像处理集成电路器件
公开(公告)号：US5027423A
公开(公告)日：1991-06-25
申请号：US378543
申请日：1989-07-12
申请人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： H04N1/409 , G06T5/20 , H03H17/02
CPC分类号： H03H17/0202
摘要： An image-processing integrated circuit device comprises a delay circuit and adder group, a multiplication block group, and an adder group. Image data in a window are fed to the delay circuit and adder group simultaneously row by row and then added up for every symmetrical positions in the window. The respective sums of the image data thus added up for every symmetrical positions are multiplied by corresponding coefficient data in the multiplication block group. Lastly, the respective results of multiplication obtained from the multiplication block group are added up by the adder group to thereby obtain a filter output. The delay circuit and adder group, the multiplication block group, and the adder group can be integrated to form one image-processing integrated circuit device. Accordingly, the number of parts is reduced. Further, not only the image data can be fed into the delay circuit and adder group simultaneously but also the multiplication in the multiplication block group can be carried out in parallel and simultaneously by using exclusive multiplication blocks each provided for symmetrical positions in the window. Accordingly, the speed in filtering processing becomes high.
摘要翻译：图像处理集成电路装置包括延迟电路和加法器组，乘法块组和加法器组。窗口中的图像数据逐行地馈送到延迟电路和加法器组，然后对于窗口中的每个对称位置相加。对于每个对称位置，这样相加的图像数据的各个和乘以乘法块组中的对应系数数据。最后，由加法器组相加从乘积组获得的相乘乘法结果，从而获得滤波器输出。延迟电路和加法器组，乘法块组和加法器组可以集成形成一个图像处理集成电路器件。因此，部件的数量减少。此外，不仅可以将图像数据同时馈送到延迟电路和加法器组，而且还可以并行地并行地通过使用为窗口中的对称位置提供的专用乘法块来执行乘法器组中的乘法。因此，滤波处理的速度变高。

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