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1. 发明申请

US20090294902A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090294902A1
公开(公告)日：2009-12-03
申请号：US12539723
申请日：2009-08-12
申请人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
发明人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
IPC分类号： H01L29/92 , H01L23/525 , H01L21/02
CPC分类号： H01G4/005 , H01G4/228 , H01G4/33 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively.
摘要翻译：半导体器件包括衬底，在衬底上形成的绝缘膜，形成在绝缘膜中的第一和第二导电插塞，电容器元件和布线。电容器元件包括下电极，电介质膜和上电极。下电极连接到第一插头的端部并形成在绝缘膜上，并且包括第一阻挡膜。电介质膜形成在下电极的上表面和侧表面上。上电极形成在电介质膜上，并且包括比下电极宽的第二阻挡金属膜。布线连接到第二插头的端部并形成在绝缘膜上，并且包括形成在第一层上的第一层和第二层。第一层和第二层分别包括第一和第二阻挡金属膜。

2. 发明授权

US08642400B2 Method of manufacturing semiconductor device including capacitor element 有权
标题翻译：制造包括电容器元件的半导体器件的方法
公开(公告)号：US08642400B2
公开(公告)日：2014-02-04
申请号：US13434177
申请日：2012-03-29
申请人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
发明人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
IPC分类号： H01L21/20
CPC分类号： H01G4/005 , H01G4/228 , H01G4/33 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes: forming a first metal film on an insulating film over a substrate; forming a capacitor lower electrode by patterning the first metal film; and forming a dielectric film on upper and side surfaces of the capacitor lower electrode and on the insulating film. The method further includes: forming a conductive protection film on the dielectric film; patterning the conductive protection film into a shape of covering the capacitor lower electrode; forming a capacitor dielectric film in a shape of covering the upper and side surfaces of the capacitor lower electrode, by patterning the dielectric film so that the patterned conductive protection film covers an upper surface of the capacitor dielectric film; forming a second metal film on the patterned conductive protection film; and forming a capacitor upper electrode that covers at least an upper surface of the patterned conductive protection film.
摘要翻译：一种制造半导体器件的方法包括：在衬底上的绝缘膜上形成第一金属膜; 通过图案化第一金属膜形成电容器下电极; 并且在电容器下电极的上表面和侧表面上以及绝缘膜上形成电介质膜。该方法还包括：在电介质膜上形成导电保护膜; 将导电保护膜图案化成覆盖电容器下电极的形状; 通过对所述电介质膜进行构图来形成覆盖所述电容器下电极的上表面和所述侧表面的电容器电介质膜，使得所述图案化的导电保护膜覆盖所述电容器电介质膜的上表面; 在图案化的导电保护膜上形成第二金属膜; 以及形成覆盖图案化的导电保护膜的至少上表面的电容器上电极。

3. 发明申请

US20120190154A1 SEMICONDUCTOR DEVICE INCLUDING CAPACITOR ELEMENT AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：包含电容元件的半导体器件及其制造方法
公开(公告)号：US20120190154A1
公开(公告)日：2012-07-26
申请号：US13434177
申请日：2012-03-29
申请人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
发明人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
IPC分类号： H01L21/768 , H01L21/02
CPC分类号： H01G4/005 , H01G4/228 , H01G4/33 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively.
摘要翻译：半导体器件包括衬底，在衬底上形成的绝缘膜，形成在绝缘膜中的第一和第二导电插塞，电容器元件和布线。电容器元件包括下电极，电介质膜和上电极。下电极连接到第一插头的端部并形成在绝缘膜上，并且包括第一阻挡膜。电介质膜形成在下电极的上表面和侧表面上。上电极形成在电介质膜上，并且包括比下电极宽的第二阻挡金属膜。布线连接到第二插头的端部并形成在绝缘膜上，并且包括形成在第一层上的第一层和第二层。第一层和第二层分别包括第一和第二阻挡金属膜。

4. 发明授权

US08169051B2 Semiconductor device including capacitor element and method of manufacturing the same 有权
标题翻译：包括电容器元件的半导体器件及其制造方法
公开(公告)号：US08169051B2
公开(公告)日：2012-05-01
申请号：US12539723
申请日：2009-08-12
申请人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
发明人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
IPC分类号： H01L29/92
CPC分类号： H01G4/005 , H01G4/228 , H01G4/33 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively.
摘要翻译：半导体器件包括衬底，在衬底上形成的绝缘膜，形成在绝缘膜中的第一和第二导电插塞，电容器元件和布线。电容器元件包括下电极，电介质膜和上电极。下电极连接到第一插头的端部并形成在绝缘膜上，并且包括第一阻挡膜。电介质膜形成在下电极的上表面和侧表面上。上电极形成在电介质膜上，并且包括比下电极宽的第二阻挡金属膜。布线连接到第二插头的端部并形成在绝缘膜上，并且包括形成在第一层上的第一层和第二层。第一层和第二层分别包括第一和第二阻挡金属膜。

5. 发明申请

US20110177672A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110177672A1
公开(公告)日：2011-07-21
申请号：US13075463
申请日：2011-03-30
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/762
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

6. 发明授权

US08937007B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08937007B2
公开(公告)日：2015-01-20
申请号：US13398254
申请日：2012-02-16
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/311 , H01L23/00 , H01L23/31
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

7. 发明申请

US20120149190A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120149190A1
公开(公告)日：2012-06-14
申请号：US13398254
申请日：2012-02-16
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/768
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

8. 发明授权

US08143153B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08143153B2
公开(公告)日：2012-03-27
申请号：US13075463
申请日：2011-03-30
申请人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
发明人： Kenichi Watanabe , Nobuhiro Misawa , Satoshi Otsuka
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/311
CPC分类号： H01L23/562 , H01L23/3192 , H01L23/564 , H01L24/05 , H01L2224/02166 , H01L2224/05567 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2224/05552
摘要： A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
摘要翻译：一种制造半导体器件的方法，包括：在由SiO 2膜介电常数低于介电常数的多个层间绝缘膜的叠层形成的层叠体中形成包围多层互连结构的防潮环，并且包括所述多层互连结构; 在所述层叠体之间在所述防潮环和划线之间形成凹槽，所述凹槽到达半导体衬底的表面; 形成包括Si和C作为主要成分并覆盖所述槽的侧壁表面和底表面的膜; 以及沿着所述凹槽的侧壁表面和所述底表面在所述膜上形成保护膜。

9. 发明授权

US08791570B2 Semiconductor device having a multilayer interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08791570B2
公开(公告)日：2014-07-29
申请号：US13483044
申请日：2012-05-29
申请人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L29/04
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.
摘要翻译：半导体器件包括嵌入在第一层间绝缘膜中的第一和第二导体图案以及嵌入在第二层间绝缘膜中的第三导体图案，所述第三导体图案包括主要部分和延伸部分，所述延伸部分电连接到第一导体图案通过第一通孔插头，延伸部分具有与第一导体图案相比更靠近主要部分的分支图案，分支图案经由第二通孔插塞与第二导体图案接触，每个主要部分，包括分支图案的延伸部分，第一通孔塞和形成镶嵌结构的第二通孔塞。

10. 发明授权

US08299619B2 Semiconductor device having a multilayer interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08299619B2
公开(公告)日：2012-10-30
申请号：US13015594
申请日：2011-01-28
申请人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L29/40
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second conductor pattern at a second region further away from, or closer to the third conductor pattern with regard to the first region via a second via-plug of a diameter smaller than the first via-plug, the extension part of the third conductor pattern, the first via-plug and the second via-plug form, together with the second interlayer insulation film, a dual damascene structure.
摘要翻译：半导体器件具有多层互连结构，其中所述多层互连结构至少包括形成在所述第一互连层上的第一互连层和第二互连层，所述第一互连层包括嵌入在第一层间绝缘膜中的第一导体图案，构成互连图案的一部分和嵌入第一层间绝缘膜中的第二另一互连图案，第二互连层包括嵌入第二层间绝缘膜中并构成所述互连图案的一部分的第三导体图案，第三导体图案的一部分具有延伸部分，以在与第三导体图案相同的层中延伸，第三导体图案经由第一通孔插头在延伸部分的第一区域处电连接到第一导体图案，扩展部分制作ac 通过直径小于第一通孔插头的第二通孔插头，在相对于第一区域进一步远离或接近第三导体图案的第二区域处与第二导体图案接合，第三导体图案的延伸部分导体图案，第一通孔塞和第二通孔塞形式与第二层间绝缘膜一起是双镶嵌结构。

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