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    • 2. 发明授权
    • Computer network system for packet-transferring data between computers,
network file server in computer network system and data transferring
method thereof
    • 计算机网络系统,计算机网络系统中的网络文件服务器和数据传输方法
    • US6014695A
    • 2000-01-11
    • US971899
    • 1997-11-17
    • Hirofumi YamashitaYoshihiro TakiyasuMitsuo AsaiNozomu HiroseMiho IwanagaRyuichi OhnoTakeshi Onodera
    • Hirofumi YamashitaYoshihiro TakiyasuMitsuo AsaiNozomu HiroseMiho IwanagaRyuichi OhnoTakeshi Onodera
    • H04N5/765H04L29/06H04N5/222H04N5/781H04N7/173H04N21/21H04N21/27G06F15/16
    • H04L49/9047H04L29/06H04L49/90H04L49/901H04L29/06027H04L67/42
    • When an access request is generated from a client in a network file server comprising a computer including a communication controller connected to at least one client through a network and transferring information on a plurality of addresses inside a main storage device as one packet to at least one client, the main storage device having a buffer, a central processing unit and an input/output bus for mutually connecting the communication controller, the central processing unit and the main storage device, and a secondary storage device connected to the computer, an area for storing the data corresponding to this access request is allocated into the buffer of the main storage device. The data corresponding to the access request is read out from the secondary storage device, is transferred to the buffer and is stored in the allocated area. A header for the data in the allocated area in the buffer, the address and size of the header and the address and size of the data are generated in the main storage device on the basis of the access request. As the address and size of the header and the address and size of the data are reported to the communication controller, the data inside the allocated area in the buffer are transferred as one packet to at least one client by the communication controller.
    • 当从包括通过网络连接到至少一个客户端的通信控制器的计算机的网络文件服务器中的客户端生成访问请求时,将作为一个分组的主存储设备内的多个地址上的信息作为一个分组传送到至少一个 客户端,具有缓冲器的主存储设备,中央处理单元和用于相互连接通信控制器,中央处理单元和主存储设备的输入/输出总线以及连接到计算机的辅助存储设备,用于 存储对应于该访问请求的数据被分配到主存储装置的缓冲器中。 从辅助存储装置读出对应于访问请求的数据,被传送到缓冲器并被存储在所分配的区域中。 基于访问请求,在主存储装置中生成用于缓冲器中的分配区域中的数据的头部,头部的地址和大小以及数据的地址和大小。 由于报头的地址和大小以及数据的地址和大小被报告给通信控制器,因此通信控制器将缓冲区内的分配区域内的数据作为一个分组传送给至少一个客户端。
    • 5. 发明授权
    • High speed clock distribution system
    • 高速时钟分配系统
    • US5087829A
    • 1992-02-11
    • US443503
    • 1989-12-01
    • Kenichi IshibashiTakehisa HayashiToshio DoiMitsuo AsaiNoboru MasudaAkira YamagiwaToshihiro Okabe
    • Kenichi IshibashiTakehisa HayashiToshio DoiMitsuo AsaiNoboru MasudaAkira YamagiwaToshihiro Okabe
    • H03K5/15
    • H03K5/15
    • This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.
    • 本发明公开了一种时钟分配系统,其将作为基准时钟的第一时钟信号作为相位和频率的参考分配给每个处理单元(例如,LSI),并且通过以下方式生成要在每个处理单元中使用的多相第二时钟信号: 延迟时间被调整的延迟电路组。 时钟分配系统包括用于产生单相参考时钟的时钟产生模块; 第一控制环路,用于将参考时钟的相位与反馈信号的相位进行比较,并且调整参考时钟的相位,使得它们的相位一致; 以及包括由多个可变延迟电路组成的延迟电路组的第二控制回路,所述多个可变延迟电路输入由第一控制回路相位调整的参考时钟并串联连接的参考时钟,以及用于产生多相时钟信号的装置 通过使用多个可变延迟电路中的每一个的输出信号和相位调整参考时钟,控制多个可变延迟电路的延迟时间,以便与相位调整参考的周期完成预定的关系 时钟,并将多相时钟信号中的一个作为上述反馈信号施加到第一控制回路。