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1. 发明申请

US20070001690A1 Probe 失效
标题翻译：探测
公开(公告)号：US20070001690A1
公开(公告)日：2007-01-04
申请号：US10553064
申请日：2004-04-13
申请人： Tetsuji Ueno , Yoshihiro Hirata , Kazunori Okada , Kazunori Kawase
发明人： Tetsuji Ueno , Yoshihiro Hirata , Kazunori Okada , Kazunori Kawase
IPC分类号： G01R31/02
CPC分类号： G01R1/06733
摘要： It is an object of the present invention to provide a beam splitter providing a high-contrast image and preventing light from scattering, and a laser scanning microscope provided with the above, in which there is provided a high-quality probe coming in contact with an electrode pad of a semiconductor device, in which a foreign substance is not likely to attach, a configuration is not likely changed and a preferable electrical contact can be maintained for a long time. According to the present invention, a probe coming into contact with an electrode pad of a measurement object comprises a connection terminal part integrally formed and connected to a substrate, a contact part having a tapered configuration, and a supporting part which supports the contact part. The contact part extending from an end of the supporting part has a sectional configuration which shares at least one side face with the supporting part.
摘要翻译：本发明的目的是提供一种提供高对比度图像并防止光散射的分束器，以及具有上述的激光扫描显微镜，其中提供了与由于外部物质不易附着的半导体器件的电极焊盘，因此不会发生形态变化，并且能够长时间保持优选的电接触。根据本发明，与测量对象的电极焊盘接触的探针包括一体地形成并连接到基板的连接端子部分，具有锥形构造的接触部分和支撑接触部分的支撑部分。从支撑部的端部延伸的接触部具有与支撑部分共享至少一个侧面的截面构造。

2. 发明授权

US07432726B2 Probe 失效
标题翻译：探测
公开(公告)号：US07432726B2
公开(公告)日：2008-10-07
申请号：US10553064
申请日：2004-04-13
申请人： Tetsuji Ueno , Yoshihiro Hirata , Kazunori Okada , Kazunori Kawase
发明人： Tetsuji Ueno , Yoshihiro Hirata , Kazunori Okada , Kazunori Kawase
IPC分类号： G01R31/02
CPC分类号： G01R1/06733
摘要： According to an embodiment, a probe coming into contact with an electrode pad of a measurement object comprises a connection terminal part integrally formed and connected to a substrate, a contact part having a tapered configuration, and a supporting part which supports the contact part. The contact part extending from an end of the supporting part has a sectional configuration which shares at least one side face with the supporting part.
摘要翻译：根据实施例，与测量对象的电极焊盘接触的探针包括一体形成并连接到基板的连接端子部分，具有锥形构造的接触部分和支撑接触部分的支撑部件。从支撑部的端部延伸的接触部具有与支撑部分共享至少一个侧面的截面构造。

3. 发明申请

US20070054457A1 Method of fabricating MOS transistor having epitaxial region 有权
标题翻译：制造具有外延区域的MOS晶体管的方法
公开(公告)号：US20070054457A1
公开(公告)日：2007-03-08
申请号：US11517246
申请日：2006-09-08
申请人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee
发明人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/66636
摘要： Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects. The method of manufacturing a MOS transistor having an epitaxial region may include forming a gate pattern on a semiconductor substrate, forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask, forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask and partially etching a lower portion of sidewalls of the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.
摘要翻译：示例实施例涉及制造半导体器件的方法。其他示例实施例涉及制造具有设置在栅极图案的侧壁的下部中的外延区域的金属氧化物半导体（MOS）晶体管的方法。提供一种制造具有提高外延生长速率并且可能具有较少缺陷的外延区域的MOS晶体管的方法。制造具有外延区域的MOS晶体管的方法可以包括在半导体衬底上形成栅极图案，通过使用栅极图案作为离子注入，将第一杂质离子注入到半导体衬底中，形成具有第一损伤分布的第一离子注入区域通过使用所述栅极图案作为离子注入掩模将所述第二杂质离子注入到所述半导体衬底中，形成具有与所述第一损伤分布相邻的第二损伤分布的第二离子注入区，并部分地蚀刻所述栅极图案的侧壁的下部;以及在蚀刻的半导体衬底上原位形成外延区域。

4. 发明授权

US07952147B2 Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same 有权
标题翻译：具有具有改善的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法
公开(公告)号：US07952147B2
公开(公告)日：2011-05-31
申请号：US11802281
申请日：2007-05-22
申请人： Tetsuji Ueno , Hwa-sung Rhee , Ho Lee
发明人： Tetsuji Ueno , Hwa-sung Rhee , Ho Lee
IPC分类号： H01L21/70
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/4933 , H01L29/665 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.
摘要翻译：具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

5. 发明授权

US07714394B2 CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same 有权
标题翻译：具有升高的源极和漏极区域的CMOS半导体器件及其制造方法
公开(公告)号：US07714394B2
公开(公告)日：2010-05-11
申请号：US11285978
申请日：2005-11-23
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L23/58
CPC分类号： H01L29/7834 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.
摘要翻译：提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。第一和第二栅极图案分别设置成跨越第一和第二有源区域。第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。还提供了制造CMOS器件的方法。

6. 发明授权

US07611951B2 Method of fabricating MOS transistor having epitaxial region 有权
标题翻译：制造具有外延区域的MOS晶体管的方法
公开(公告)号：US07611951B2
公开(公告)日：2009-11-03
申请号：US11517246
申请日：2006-09-08
申请人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee
发明人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/66636
摘要： Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects. The method of manufacturing a MOS transistor having an epitaxial region may include forming a gate pattern on a semiconductor substrate, forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask, forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask and partially etching a lower portion of sidewalls of the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.
摘要翻译：示例实施例涉及制造半导体器件的方法。其他示例实施例涉及制造具有设置在栅极图案的侧壁的下部中的外延区域的金属氧化物半导体（MOS）晶体管的方法。提供一种制造具有提高外延生长速率并且可能具有较少缺陷的外延区域的MOS晶体管的方法。制造具有外延区域的MOS晶体管的方法可以包括在半导体衬底上形成栅极图案，通过使用栅极图案作为离子注入，将第一杂质离子注入到半导体衬底中，形成具有第一损伤分布的第一离子注入区域通过使用所述栅极图案作为离子注入掩模将所述第二杂质离子注入到所述半导体衬底中，形成具有与所述第一损伤分布相邻的第二损伤分布的第二离子注入区，并部分地蚀刻所述栅极图案的侧壁的下部;以及在蚀刻的半导体衬底上原位形成外延区域。

7. 发明授权

US07361563B2 Methods of fabricating a semiconductor device using a selective epitaxial growth technique 有权
标题翻译：使用选择性外延生长技术制造半导体器件的方法
公开(公告)号：US07361563B2
公开(公告)日：2008-04-22
申请号：US11299447
申请日：2005-12-09
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/205 , H01L29/80 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.
摘要翻译：使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。将具有凹部的基板装入反应室。将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

8. 发明申请

US20080067545A1 Semiconductor device including field effect transistor and method of forming the same 审中-公开
标题翻译：包括场效晶体管的半导体器件及其形成方法
公开(公告)号：US20080067545A1
公开(公告)日：2008-03-20
申请号：US11898978
申请日：2007-09-18
申请人： Hwa-sung Rhee , Tetsuji Ueno , Ho Lee , Myung-sun Kim , Ji-hye Yi
发明人： Hwa-sung Rhee , Tetsuji Ueno , Ho Lee , Myung-sun Kim , Ji-hye Yi
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L21/26513 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device having a field effect transistor according to example embodiments may include a first semiconductor pattern disposed to fill a first recess region and a second semiconductor pattern disposed to fill a second recess region. The first recess region may be shallower than the second recess region and may be disposed adjacent to a channel region. Thus, sufficient stress may be supplied to the channel region to increase the mobility of holes or carriers in a channel and enhance a punchthrough characteristic.
摘要翻译：具有根据示例实施例的场效应晶体管的半导体器件可以包括设置成填充第一凹陷区域的第一半导体图案和设置成填充第二凹陷区域的第二半导体图案。第一凹部区域可以比第二凹部区域浅，并且可以设置在与沟道区域相邻的位置。因此，可以向通道区域提供足够的应力以增加通道中的空穴或载流子的迁移率并增强穿透特性。

9. 发明申请

US20060156970A1 Methods for in-situ cleaning of semiconductor substrates and methods of semiconductor device fabrication employing the same 审中-公开
标题翻译：用于半导体衬底的原位清洁的方法和使用其的半导体器件制造方法
公开(公告)号：US20060156970A1
公开(公告)日：2006-07-20
申请号：US11232955
申请日：2005-09-23
申请人： Shin Dong-Suk , Tetsuji Ueno , Lee Seung-Hwan , Lee Ho , Rhee Hwa-Sung
发明人： Shin Dong-Suk , Tetsuji Ueno , Lee Seung-Hwan , Lee Ho , Rhee Hwa-Sung
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： C30B25/18
摘要： Provided is an in-situ precleaning method for use in conjunction with epitaxial processes that utilizes temperatures at or below those typically utilized during the subsequent epitaxial deposition under pressure and ambient conditions suitable for inducing decomposition of semiconductor oxides, such as native oxides, from exposed semiconductor surfaces. The reduced temperature and the resulting quality of the cleaned semiconductor surfaces will tend to reduce the likelihood of temperature related issues such as unwanted diffusion, autodoping, slip, and other crystalline stress problems while simultaneously reducing the overall process time. The combination of pressure, ambient gas composition and temperature maintained within the reaction chamber are sufficient to decompose semiconductor oxides present on the substrate surface. For example, the reaction chamber may be operated so that the concentration of evolved oxygen within the reaction chamber is less than about 50%, or even less than 10%, of the equilibrium vapor pressure under the cleaning conditions.
摘要翻译：提供了一种与外延工艺结合使用的原位预清洗方法，该外延工艺利用在随后的外延沉积期间通常利用的温度等于或低于在压力和环境条件下适合于从暴露的半导体分解半导体氧化物（例如天然氧化物）的环境条件下的温度表面。清洁的半导体表面的降低的温度和所得到的质量倾向于降低诸如不期望的扩散，自掺杂，滑移和其它结晶应力问题之类的温度相关问题的可能性，同时减少整个处理时间。压力，环境气体组成和保持在反应室内的温度的组合足以分解存在于基板表面上的半导体氧化物。例如，可以操作反应室，使得在清洁条件下，反应室内的放出的氧气的浓度小于平衡蒸汽压力的约50％，甚至小于10％。

10. 发明申请

US20050279997A1 Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same 有权
标题翻译：在使用其制造的单晶半导体和半导体器件上选择性地形成外延半导体层的方法
公开(公告)号：US20050279997A1
公开(公告)日：2005-12-22
申请号：US11154236
申请日：2005-06-16
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/20 , H01L21/205 , H01L21/28 , H01L21/336 , H01L29/772
CPC分类号： H01L21/28044 , H01L21/02378 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/66628 , H01L29/66772
摘要： In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.
摘要翻译：在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中，单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶半导体图案，分别使用主半导体源气体和主蚀刻气体。使用选择性蚀刻气体去除非单晶外延半导体层。主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

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