会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same
    • 具有升高的源极和漏极区域的CMOS半导体器件及其制造方法
    • US20060131656A1
    • 2006-06-22
    • US11285978
    • 2005-11-23
    • Dong-Suk ShinHwa-Sung RheeTetsuji UenoHo LeeSeung-Hwan Lee
    • Dong-Suk ShinHwa-Sung RheeTetsuji UenoHo LeeSeung-Hwan Lee
    • H01L29/94
    • H01L29/7834H01L21/265H01L21/823807H01L21/823814H01L29/665H01L29/6653H01L29/6656H01L29/66628
    • A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.
    • 提供互补金属氧化物半导体(CMOS)器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。 第一和第二栅极图案分别设置成跨越第一和第二有源区域。 第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧,并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。 第一升高的源极/漏极区域设置在第一有源区上,而第二升高的源极/漏极区域设置在第二有源区域上。 在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。 设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。 还提供了制造CMOS器件的方法。
    • 7. 发明授权
    • Method of forming MOS transistor having fully silicided metal gate electrode
    • 形成具有完全硅化金属栅电极的MOS晶体管的方法
    • US07582535B2
    • 2009-09-01
    • US11158978
    • 2005-06-22
    • Seung-Hwan LeeDong-Suk ShinHwa-Sung RheeTetsuji UenoHo Lee
    • Seung-Hwan LeeDong-Suk ShinHwa-Sung RheeTetsuji UenoHo Lee
    • H01L21/336
    • H01L29/4975H01L21/28097H01L21/823835H01L21/823842H01L29/665H01L29/6653H01L29/66545H01L29/6656H01L29/66628H01L29/66636
    • Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions. Respective desired thicknesses of the gate-reduced pattern and the elevated source and drain regions may be obtained using an etch selectivity between the poly-crystalline semiconductor layer and the single-crystalline semiconductor layer. A silicidation process is applied to the semiconductor substrate where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.
    • 提供制造具有完全硅化金属栅电极的MOS晶体管的方法。 该方法包括在半导体衬底的预定区域中形成隔离层以限定有源区。 形成了跨越有源区域的绝缘栅极图案。 在栅极图案的侧壁上形成间隔物。 施加选择性外延生长工艺以在栅极图案上形成半导体层,并且在栅极图案的两侧形成半导体层。 在这种情况下,在栅极图案上形成多晶半导体层,同时在栅极图案的两侧的有源区同时形成单晶半导体层。 选择性地蚀刻半导体层以形成栅极减小图案和升高的源极和漏极区域。 可以使用多晶半导体层和单晶半导体层之间的蚀刻选择性来获得栅极减小图案和升高的源极和漏极区域的各种期望厚度。 将硅化处理应用于形成栅极减少图案的半导体衬底,以同时形成完全硅化的金属栅电极和升高的源极和漏极硅化物层。
    • 9. 发明授权
    • CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same
    • 具有升高的源极和漏极区域的CMOS半导体器件及其制造方法
    • US07714394B2
    • 2010-05-11
    • US11285978
    • 2005-11-23
    • Dong-Suk ShinHwa-Sung RheeTetsuji UenoHo LeeSeung-Hwan Lee
    • Dong-Suk ShinHwa-Sung RheeTetsuji UenoHo LeeSeung-Hwan Lee
    • H01L23/58
    • H01L29/7834H01L21/265H01L21/823807H01L21/823814H01L29/665H01L29/6653H01L29/6656H01L29/66628
    • A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.
    • 提供互补金属氧化物半导体(CMOS)器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。 第一和第二栅极图案分别设置成跨越第一和第二有源区域。 第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧,并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。 第一升高的源极/漏极区域设置在第一有源区上,而第二升高的源极/漏极区域设置在第二有源区域上。 在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。 设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。 还提供了制造CMOS器件的方法。