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1. 发明授权

US5678062A Input/output control method and data processor 失效
标题翻译：输入/输出控制方法和数据处理器
公开(公告)号：US5678062A
公开(公告)日：1997-10-14
申请号：US199889
申请日：1994-02-22
申请人： Tetsuhiko Okada , Hideki Murayama , Takehisa Hayashi , Atsushi Ugajin , Yasuhiro Ishii , Masahiro Kitano
发明人： Tetsuhiko Okada , Hideki Murayama , Takehisa Hayashi , Atsushi Ugajin , Yasuhiro Ishii , Masahiro Kitano
IPC分类号： G06F13/12 , G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A system for controlling the DMA transfer for a plurality of IO devices has an IO controller for each group of the IO devices. Data is retrieved from memory and stored in the IO controller where it is analyzed. The retrieved data has a structure that permits a group of DMA start request quads to be linked together for parallel or pipeline processing of the DMA transfer requests. Each start request quad has a pointer for additionally retrieving corresponding command data. The command data is set forth in a number of blocks, each linked to the next one by a pointer. When a DMA processing has been completed, the termination or completion status is entered into a specific entry in a completion list for the corresponding IO device. Thus, a determination can be made as to whether specific IO devices have completed a requested DMA processing. Expansion of the system is accomplished by using combinations of main and sub controllers, where one main controller provides the aforementioned data structures for many sub controllers in order to enable the DMA processing to be performed for IO devices connected to the sub controllers with less frequent access of system main memory and the system bus.
摘要翻译：用于控制多个IO设备的DMA传输的系统具有用于每组IO设备的IO控制器。数据从存储器检索并存储在IO控制器中进行分析。检索的数据具有允许一组DMA启动请求四元组链接在一起以用于DMA传送请求的并行或流水线处理的结构。每个启动请求四元组都有一个指针，用于附加地检索相应的命令数据。命令数据在多个块中设置，每个块通过指针链接到下一个块。当DMA处理完成时，终止或完成状态将被输入到对应的IO设备的完成列表中的特定条目中。因此，可以确定特定的IO设备是否已经完成了所请求的DMA处理。通过使用主控制器和副控制器的组合来实现系统的扩展，其中一个主控制器为许多子控制器提供上述数据结构，以便能够对连接到具有较少频率访问的子控制器的IO设备执行DMA处理的系统主存和系统总线。

2. 发明授权

US06728258B1 Multi-processor system and its network 失效
标题翻译：多处理器系统及其网络
公开(公告)号：US06728258B1
公开(公告)日：2004-04-27
申请号：US09456383
申请日：1999-12-08
申请人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
发明人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
IPC分类号： H04L1266
CPC分类号： G06F15/17375 , G06F12/0833 , G06F2212/1016 , G06F2212/206
摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.
摘要翻译：在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路请求以下列方式。对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。

3. 发明授权

US6011791A Multi-processor system and its network 失效
标题翻译：多处理器系统及其网络
公开(公告)号：US6011791A
公开(公告)日：2000-01-04
申请号：US747344
申请日：1996-11-12
申请人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
发明人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
IPC分类号： G06F15/173 , G06F13/38 , H04L12/56
CPC分类号： G06F15/17375
摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.
摘要翻译：在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路请求以下列方式。对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。

4. 发明授权

US06049221A Semiconductor integrated circuit system having function of automatically adjusting output resistance value 失效
标题翻译：具有自动调节输出电阻值功能的半导体集成电路系统
公开(公告)号：US06049221A
公开(公告)日：2000-04-11
申请号：US111804
申请日：1998-07-08
申请人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Hideki Murayama , Akira Yamagiwa , Yasuhiro Ishii , Naoki Hamanaka , Masabumi Shibata
发明人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Hideki Murayama , Akira Yamagiwa , Yasuhiro Ishii , Naoki Hamanaka , Masabumi Shibata
IPC分类号： H03K19/003 , H03K19/00 , H03K19/0175 , H04L25/02 , H03K19/175
CPC分类号： H03K19/0005
摘要： A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.
摘要翻译：具有参照正在运行的LSI的温度来自动调整输出电阻值的功能的半导体集成电路系统。当通过对计时器的输出进行计数而得到的计数值等于预定值时，温度传感器测量LSI的温度。如果从先前测量值测量的温度波动大于预定宽度，则控制装置发出输出电阻值调整请求信号以输出LSI的电阻调节单元。当接收到输出电阻值调整请求信号时，输出电阻值调节单元停止LSI之间的信号传输，以输出电阻值与传输线的特性阻抗匹配的方式调整输出电路的输出电阻值并保持调整后的输出电阻值直到输出电阻值调整单元接收到下一个输出电阻值调整请求信号。

5. 发明授权

US07080227B2 Information processing apparatus 失效
公开(公告)号：US07080227B2
公开(公告)日：2006-07-18
申请号：US10062503
申请日：2002-02-05
申请人： Hideki Murayama , Kazuo Horikawa , Hiroshi Yashiro , Masahiko Yamauchi , Yasuhiro Ishii , Daisuke Sasaki
发明人： Hideki Murayama , Kazuo Horikawa , Hiroshi Yashiro , Masahiko Yamauchi , Yasuhiro Ishii , Daisuke Sasaki
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0646 , G06F12/10
摘要： An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.

6. 发明授权

US07062627B2 Memory managing method used in adding memory and information processing apparatus 失效
标题翻译：用于添加内存和信息处理设备的内存管理方法
公开(公告)号：US07062627B2
公开(公告)日：2006-06-13
申请号：US10642644
申请日：2003-08-19
申请人： Hideki Murayama , Kazuo Horikawa , Hiroshi Yashiro , Masahiko Yamauchi , Yasuhiro Ishii , Daisuke Sasaki
发明人： Hideki Murayama , Kazuo Horikawa , Hiroshi Yashiro , Masahiko Yamauchi , Yasuhiro Ishii , Daisuke Sasaki
IPC分类号： G06F12/00
CPC分类号： G06F12/0646 , G06F12/10
摘要： An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
摘要翻译：一种信息处理装置，用于在被供电时允许添加存储器。该装置包括处理器，初始连接的第一主存储器和连接开关。交换机连接处理器，第一主存储器和要添加的第二主存储器。第一主存储器中的主存储器管理信息包括连接到处理器的存储器资源的大小。连接开关中的存储区域保持关于处理器是否连接到每个存储器的信息。该设置允许设备使用添加的内存，而无需重新启动。

7. 发明授权

US06684312B1 Memory managing method used in adding memory and information processing apparatus 失效
标题翻译：用于添加内存和信息处理设备的内存管理方法
公开(公告)号：US06684312B1
公开(公告)日：2004-01-27
申请号：US09227740
申请日：1999-01-08
申请人： Hideki Murayama , Kazuo Horikawa , Hiroshi Yashiro , Masahiko Yamauchi , Yasuhiro Ishii , Daisuke Sasaki
发明人： Hideki Murayama , Kazuo Horikawa , Hiroshi Yashiro , Masahiko Yamauchi , Yasuhiro Ishii , Daisuke Sasaki
IPC分类号： G06F1200
CPC分类号： G06F12/0646 , G06F12/10
摘要： An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
摘要翻译：一种信息处理装置，用于在被供电时允许添加存储器。该装置包括处理器，初始连接的第一主存储器和连接开关。交换机连接处理器，第一主存储器和要添加的第二主存储器。第一主存储器中的主存储器管理信息包括连接到处理器的存储器资源的大小。连接开关中的存储区域保持关于处理器是否连接到每个存储器的信息。该设置允许设备使用添加的内存，而无需重新启动。

8. 发明授权

US08779320B2 Resistance welding method, resistance welder, and method and device for evaluating resistance welding 有权
标题翻译：电阻焊接方法，电阻焊机以及电阻焊接评估方法和装置
公开(公告)号：US08779320B2
公开(公告)日：2014-07-15
申请号：US13060363
申请日：2010-07-20
申请人： Goro Watanabe , Yasuhiro Ishii , Yasumoto Sato , Tsunaji Kitayama , Hisaaki Takao , Hideki Teshima , Keisuke Uchida
发明人： Goro Watanabe , Yasuhiro Ishii , Yasumoto Sato , Tsunaji Kitayama , Hisaaki Takao , Hideki Teshima , Keisuke Uchida
IPC分类号： B23K11/00
CPC分类号： B23K11/256 , B23K11/115
摘要： Exemplary embodiments provide a resistance welding method capable of stabilizing quality or improving efficiency of resistance welding such as spot welding. This resistance welding method comprises a calculating step of calculating resistance ratio X of a second electric resistance value R2 of workpieces to be joined in residual heat after Joule heating stops to a first electric resistance value R1 of the workpieces immediately before the Joule heating stops or vice versa (R2/R1 or R1/R2); a determining step of determining whether the resistance ratio X is equal to or greater than a threshold value Xn, and a reheating step of carrying out the Joule heating again when the resistance ratio X is smaller than the threshold value Xn. Thereby at least part of a welding portion is melted and solidified to reliably form a nugget, and a stably resistance-welded member can be provided.
摘要翻译：示例性实施例提供能够稳定质量或提高诸如点焊的电阻焊接效率的电阻焊接方法。该电阻焊接方法包括以下计算步骤：在焦耳加热停止之后，在焦耳加热停止后的剩余热量中要连接的工件的第二电阻值R2的电阻比X计算到刚巧焦耳加热停止之前的工件的第一电阻值R1 （R2 / R1或R1 / R2）; 确定电阻比X是否等于或大于阈值Xn的确定步骤，以及当电阻比X小于阈值Xn时再次进行焦耳加热的再加热步骤。由此，焊接部的至少一部分熔融固化，可靠地形成熔核，并且可以提供稳定的电阻焊接部件。

9. 发明授权

US08141413B2 Particulate matter concentration measuring apparatus 有权
标题翻译：颗粒物浓度测定仪
公开(公告)号：US08141413B2
公开(公告)日：2012-03-27
申请号：US12694291
申请日：2010-01-27
申请人： Athanasios G. Konstandopoulos , Fumishige Miyata , Takafumi Kasuga , Yasuhiro Ishii
发明人： Athanasios G. Konstandopoulos , Fumishige Miyata , Takafumi Kasuga , Yasuhiro Ishii
IPC分类号： G01M15/10
CPC分类号： G01N15/0618 , F01N3/021 , F01N3/031 , F01N11/00 , F01N2550/04 , F01N2560/05 , F01N2560/06 , G01N1/2252 , Y02T10/47
摘要： A particulate matter concentration measuring apparatus is configured to measure a concentration of particulate matter in exhaust gas flowing through an exhaust line of a diesel engine. The apparatus includes an exhaust gas extraction line diverging from the exhaust line and having a flow passage cross-sectional area smaller than a flow passage cross-sectional area of the exhaust line. A particulate matter detection filter has a cell wall and is provided in the exhaust gas extraction line. A flow velocity of the exhaust gas passing through the cell wall is more than or equal to approximately 0.02 m/s and less than or equal to approximately 2.0 m/s. A differential pressure sensing part is configured to sense a differential pressure generated between an inlet and an outlet of the particulate matter detection filter.
摘要翻译：颗粒物浓度测量装置被配置为测量流经柴油发动机的排气管线的废气中的颗粒物质的浓度。该装置包括从排气管线分流并具有小于排气管路的流路横截面积的流路截面积的废气抽出管线。颗粒物检测过滤器具有细胞壁并设置在废气抽出管线中。通过细胞壁的排气的流速大于或等于约0.02m / s且小于或等于约2.0m / s。差压感测部被配置为感测在颗粒物检测过滤器的入口和出口之间产生的压差。

10. 发明授权

US5402239A Method of measuring orientation flat width of single crystal ingot 失效
标题翻译：测量单晶锭取向平面宽度的方法
公开(公告)号：US5402239A
公开(公告)日：1995-03-28
申请号：US203570
申请日：1994-03-01
申请人： Yasuhiro Ishii , Yoshihiro Hirano
发明人： Yasuhiro Ishii , Yoshihiro Hirano
IPC分类号： G01B11/00 , G01B11/02 , G01B21/02 , H01L21/66 , C01B5/02
CPC分类号： G01B11/00 , G01B11/02
摘要： Disclosed is a method of measuring the OF width of a cylindrical single crystal ingot using an optical non-contact type displacement measuring device. This method can avoid the labor and measurement errors as generally seen in the conventional manual method and provide an easy and precise measurement. Further, the method can be automated if necessary. This method comprises the steps of detecting the boundary points between the OF and the round surface of the single crystal ingot from the displacement to be obtained by scanning the sensor while detecting the distance between the sensor and the ingot surface including the OF, and calculating the OF width C from the scanning distance A of the sensor from the first boundary point detection position to the second boundary point detection position and the difference B between the first distance 1.sub.1 from the first boundary point to the sensor and the second distance 1.sub.2 from the sensor to the second boundary point.
摘要翻译：公开了使用光学非接触型位移测量装置测量圆柱形单晶锭的OF宽度的方法。这种方法可以避免常规手动方法中普遍看到的劳动和测量误差，并提供简单而精确的测量。此外，如果需要，该方法可以自动化。该方法包括以下步骤：通过扫描传感器同时检测包括OF的传感器和锭块表面之间的距离，从单位晶圆的圆周面到边界点之间的边界点，从而计算出 OF宽度C从传感器的扫描距离A从第一边界点检测位置到第二边界点检测位置，以及从第一边界点到传感器的第一距离11与传感器的第二距离12之间的差B 到第二个边界点。

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