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1. 发明授权

US4499484A Integrated circuit manufactured by master slice method 失效
标题翻译：集成电路采用主片法制作
公开(公告)号：US4499484A
公开(公告)日：1985-02-12
申请号：US415795
申请日：1982-09-08
申请人： Tetsu Tanizawa , Hitoshi Omichi , Yoshiharu Mitono
发明人： Tetsu Tanizawa , Hitoshi Omichi , Yoshiharu Mitono
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L23/528 , H01L27/04 , H01L27/118 , H01L21/70 , H01L21/90 , H01L29/44
CPC分类号： H01L23/528 , H01L21/82 , H01L23/5286 , H01L24/06 , H01L27/118 , H01L2924/14
摘要： In an integrated circuit manufactured by the master slice method, the feeder line for supplying electric power to a unit-cell array is gradually narrowed in width from the periphery to the middle of the array. As a result, sufficient voltage is supplied to the unit-cells at the middle of the IC and an area of an interconnecting domain for connecting the unit-cells is expanded.
摘要翻译：在通过主分片方法制造的集成电路中，用于向单元阵列提供电力的馈线从阵列的周边到中间的宽度逐渐变窄。结果，向集成电路的中间的单位电池供给足够的电压，扩大连接单位电池的互联域的面积。

2. 发明授权

US4523106A Integrated circuit having predetermined outer to inner cell pitch ratio 失效
标题翻译：具有预定的外部与内部单元间距比的集成电路
公开(公告)号：US4523106A
公开(公告)日：1985-06-11
申请号：US411269
申请日：1982-08-25
申请人： Tetsu Tanizawa , Hitoshi Omichi , Yoshiharu Mitono
发明人： Tetsu Tanizawa , Hitoshi Omichi , Yoshiharu Mitono
IPC分类号： H01L21/822 , G11C5/02 , H01L21/82 , H01L27/04 , H01L27/118 , H03K19/173 , H03K19/177 , H03K3/26 , H01J37/28
CPC分类号： H03K19/17744 , G11C5/025 , H01L24/06 , H01L27/11898 , H03K19/1732 , H03K19/17796 , H01L2224/0603 , H01L2924/14 , Y10S257/923
摘要： An integrated circuit device such as a gate array or a master slice LSI device which is formed on a semiconductor chip and which comprises an inner cell array including a plurality of inner cells, an outer cell array including a plurality of outer cells formed around the inner cell array, a power supply portion having one or more outer power supply lines, and a plurality of inner power supply lines connected to the outer power supply lines and formed on the inner cell array. The ratio of the pitch length of the outer cells to the pitch length of the inner power supply lines or the inner cells is determined by the ratio of two integers. In the integrated circuit device, at least one set of an outer cell, and an inner cell which are arranged in a predetermined positional relation, is formed a plurality of times along a side of the semiconductor chip.
摘要翻译：一种集成电路装置，例如门阵列或主切片LSI装置，其形成在半导体芯片上，并且包括：内单元阵列，包括多个内单元;外单元阵列，包括围绕内部的多个外单元; 电池阵列，具有一个或多个外部电源线的电源部分和连接到外部电源线并形成在内部单元阵列上的多个内部电源线。外部单元的音调长度与内部电源线或内部单元的音调长度的比率由两个整数的比率确定。在集成电路器件中，沿着半导体芯片的一侧多次形成以预定位置关系布置的至少一组外部单元和内部单元。

3. 发明授权

US4868630A Gate array semiconductor integrated circuit 失效
标题翻译：门阵列半导体集成电路
公开(公告)号：US4868630A
公开(公告)日：1989-09-19
申请号：US769800
申请日：1985-08-27
申请人： Tetsu Tanizawa , Yoshiharu Mitono , Hitoshi Omichi
发明人： Tetsu Tanizawa , Yoshiharu Mitono , Hitoshi Omichi
IPC分类号： H01L23/528 , H01L27/118
CPC分类号： H01L27/11898 , H01L23/528 , H01L2924/0002
摘要： A semiconductor integrated circuit including at least one conventional inner cell region and an outer cell region. The outer cell region comprising a plurality of outer cells. Each outer cell is comprised of circuit elements for achieving a predetermined logic function, in addition to circuit elements for achieving the conventional buffer function of an outer cell. Further, two or more adjacent outer cells are connected each other and act as an independent circuit so as to form a macro-cell.
摘要翻译：一种半导体集成电路，包括至少一个常规内部单元区域和外部单元区域。外细胞区域包括多个外细胞。除了用于实现外部单元的常规缓冲功能的电路元件之外，每个外部单元包括用于实现预定逻辑功能的电路元件。此外，两个或更多个相邻的外部单元彼此连接，并且用作独立的电路以形成宏单元。

4. 发明授权

US4564773A Semiconductor gate array device having an improved interconnection structure 失效
标题翻译：具有改进的互连结构的半导体门阵列器件
公开(公告)号：US4564773A
公开(公告)日：1986-01-14
申请号：US407148
申请日：1982-08-11
申请人： Tetsu Tanizawa , Hitoshi Omichi , Yoshiharu Mitono
发明人： Tetsu Tanizawa , Hitoshi Omichi , Yoshiharu Mitono
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118 , H03K19/173 , H03K19/177 , H01L27/00 , H03K19/003 , H03K19/088
CPC分类号： H03K19/17748 , H01L27/11801 , H03K19/1735 , H03K19/17704 , H03K19/17728 , H03K19/17736 , Y10S257/923
摘要： In a semiconductor device having a gate array structure, a macro-cell includes more basic cells than conventional macro-cells, for preforming a logic function, whereby the density of the terminals in a direction vertical to a direction in which wiring lines are drawn, is decreased.
摘要翻译：在具有门阵列结构的半导体器件中，宏单元包括比常规宏单元更多的基本单元，用于预处理逻辑功能，由此在垂直于布线的方向的方向上的端子的密度，减少。

5. 发明授权

US4388755A Structure for and method of manufacturing a semiconductor device by the master slice method 失效
标题翻译：通过主切片方法制造半导体器件的结构和方法
公开(公告)号：US4388755A
公开(公告)日：1983-06-21
申请号：US207737
申请日：1980-11-17
申请人： Hiromu Enomoto , Yasushi Yasuda , Yoshiharu Mitono , Taketo Imaizumi , Hitoshi Ohmichi
发明人： Hiromu Enomoto , Yasushi Yasuda , Yoshiharu Mitono , Taketo Imaizumi , Hitoshi Ohmichi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L21/822 , H01L21/8222 , H01L23/52 , H01L27/04 , H01L27/082 , H01L27/118 , H01L29/08
CPC分类号： H01L23/52 , H01L27/11801 , H01L29/0813 , H01L2924/0002
摘要： A structure and method for manufacturing semiconductor devices by the master slice method, in which various kinds of semiconductor devices are manufactured through utilization of a common master pattern and a plurality of different kinds of selective wiring patterns. A number of bipolar transistors each having plural emitter regions, is formed in a predetermined region, or portion, of a semiconductor substrate by employing a common master pattern, and the plural emitter regions of the respective bipolar transistors are selectively connected by the associated wiring patterns of each thereof to form corresponding bipolar transistors of different, predetermined D.C. characteristics. When manufacturing many different kinds of semiconductor devices by the master slice method, the area which would be wasted on the semiconductor substrate by prior art techniques is greatly reduced, thus providing for enhanced area efficiency.
摘要翻译：通过主切片方法制造半导体器件的结构和方法，其中通过利用公共主图和多种不同种类的选择性布线图来制造各种半导体器件。每个具有多个发射极区域的多个双极晶体管通过采用公共主图案形成在半导体衬底的预定区域或部分中，并且各个双极晶体管的多个发射极区域通过相关布线图案选择性地连接以形成具有不同的预定DC特性的相应双极晶体管。当通过主分片方法制造许多不同种类的半导体器件时，通过现有技术将浪费在半导体衬底上的区域大大减少，从而提供增强的面积效率。

6. 发明授权

US4449063A Logic circuit with improved switching 失效
标题翻译：具有改进开关的逻辑电路
公开(公告)号：US4449063A
公开(公告)日：1984-05-15
申请号：US180452
申请日：1980-08-22
申请人： Hitoshi Ohmichi , Hiromu Enomoto , Yasushi Yasuda , Yoshiharu Mitono , Taketo Imaizumi
发明人： Hitoshi Ohmichi , Hiromu Enomoto , Yasushi Yasuda , Yoshiharu Mitono , Taketo Imaizumi
IPC分类号： H03K19/013 , H03K19/084 , H03K19/088
CPC分类号： H03K19/084 , H03K19/0136 , H03K19/088
摘要： A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.
摘要翻译：例如在电子计算机中使用的基本逻辑电路包括输出反相晶体管和开关晶体管，当输出反相器晶体管变化时，输出反相器晶体管的基极 - 发射极结中存储存储在存储电容中的基极电荷从开启状态到关闭状态。

7. 发明授权

US4613887A Semiconductor device with a means for discharging carriers 失效
标题翻译：具有用于放电载体的装置的半导体器件
公开(公告)号：US4613887A
公开(公告)日：1986-09-23
申请号：US574583
申请日：1984-01-27
申请人： Takeshi Fukuda , Yoshiharu Mitono , Tadashi Kiriseko
发明人： Takeshi Fukuda , Yoshiharu Mitono , Tadashi Kiriseko
IPC分类号： H01L21/761 , H01L27/07 , H01L27/082 , H01L29/06 , H01L29/10 , H03K19/088 , H01L27/04 , H03K19/013
CPC分类号： H03K19/088 , H01L21/761 , H01L27/0772 , H01L27/0821 , H01L29/0638 , H01L29/1004
摘要： In an output transistor of transistor-transistor logic (TTL) circuits, an output transistor of TTL is provided with, in a region between a p-type base region and the p-type semiconductor substrate on which a TTL circuit is fabricated, a p.sup.- diffusion which causes carriers stored in the base region when the output transistor is switched from ON state to OFF state to be discharged quickly. When the output transistor is OFF, the p.sup.- diffusion is pinched off and no current flows. Thus, when the output transistor is switched from OFF state to ON state, the output voltage changes sharply. Because of this, the switching speed of the TTL is improved. In another embodiment, a p.sup.- region is formed between a p-type base region and p.sup.+ isolation diffusion, and an n.sup.+ diffusion is formed to cover at least one part of the p.sup.- diffusion and is connected to an n-type collector region. In another embodiment, a p-type base region extends to the p.sup.+ isolation diffusion, and an n.sup.+ diffusion is formed in a region between the base region and the isolation diffusion and is connected to an n-type collector region.
摘要翻译：在晶体管晶体管逻辑（TTL）电路的输出晶体管中，TTL的输出晶体管在p型基极区域和其上制造TTL电路的p型半导体衬底之间的区域中设置有p - 当输出晶体管从接通状态切换到断开状态时，导致存储在基极区域中的载流子的扩散被快速放电。当输出晶体管截止时，p扩散被夹断，没有电流流动。因此，当输出晶体管从OFF状态切换到ON状态时，输出电压急剧变化。因此，提高了TTL的切换速度。在另一个实施例中，p区形成在p型基极区和p +隔离扩散之间，形成n +扩散以覆盖p-扩散的至少一部分并连接到n型集电极区。在另一个实施例中，p型基极区域延伸到p +隔离扩散部分，并且在基极区域和隔离扩散部分之间的区域中形成n +扩散，并连接到n型集电极区域。

8. 发明授权

US4409495A Schmitt trigger circuit with low input current 失效
标题翻译：施密特触发电路具有低输入电流
公开(公告)号：US4409495A
公开(公告)日：1983-10-11
申请号：US268643
申请日：1981-05-29
申请人： Hiromu Enomoto , Yoshiharu Mitono , Yasushi Yasuda , Taketo Imaizumi , Hiroshi Ohta
发明人： Hiromu Enomoto , Yoshiharu Mitono , Yasushi Yasuda , Taketo Imaizumi , Hiroshi Ohta
IPC分类号： H03K3/2893 , H03K5/08 , H03K3/295
CPC分类号： H03K3/2893
摘要： A Schmitt trigger circuit has an input-voltage hysteresis characteristic for reducing noise sensitivity and preventing oscillation. In its input stage there is a multi-emitter transistor, and in its output stage a second transistor. The multi-emitter transistor comprises a first emitter and a second emitter. The first emitter is associated with a switching operation in response to the input voltage applied to the base of the multi-emitter transistor. The second emitter is associated with the operation of drawing charges from the base of the second transistor through the base of the multi-emitter transistor to the ground. The use of the multi-emitter transistor prevents the input current from increasing greatly as the input voltage falls.
摘要翻译：施密特触发电路具有降低噪声灵敏度和防止振荡的输入电压滞后特性。在其输入级具有多发射极晶体管，并且在其输出级中具有第二晶体管。多发射极晶体管包括第一发射极和第二发射极。响应于施加到多发射极晶体管的基极的输入电压，第一发射极与开关操作相关联。第二发射极与从第二晶体管的基极通过多发射极晶体管的基极到地的绘制电荷的操作相关联。使用多发射极晶体管可防止输入电流随着输入电压的下降而大幅度增加。

9. 发明授权

US4276556A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4276556A
公开(公告)日：1981-06-30
申请号：US094436
申请日：1979-11-15
申请人： Hiromu Enomoto , Yasushi Yasuda , Hitoshi Ohmichi , Yoshiharu Mitono
发明人： Hiromu Enomoto , Yasushi Yasuda , Hitoshi Ohmichi , Yoshiharu Mitono
IPC分类号： H01L27/06 , H01L21/331 , H01L21/761 , H01L21/8222 , H01L27/07 , H01L29/73 , H01L29/861 , H01L29/34
CPC分类号： H01L27/0761 , H01L21/761 , H01L27/0766
摘要： A semiconductor device including a diode and a bipolar transistor which are connected to each other and formed in an isolated area of a semiconductor layer has a diffused region formed between a base region of the bipolar transistor and a formation region of the diode across the isolated area. The diffused region has the same conductivity type as that of the base region, so that a PNPN diode effect does not occur.
摘要翻译：包括彼此连接并形成在半导体层的隔离区域中的二极管和双极晶体管的半导体器件具有形成在双极晶体管的基极区域和跨越隔离区域的二极管的形成区域之间的扩散区域。扩散区域具有与基极区域相同的导电类型，使得不发生PNPN二极管效应。

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