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1. 发明授权

US5388055A Semiconductor integrated circuit having polycell structure and method of designing the same 失效
标题翻译：具有多单元结构的半导体集成电路及其设计方法
公开(公告)号：US5388055A
公开(公告)日：1995-02-07
申请号：US756017
申请日：1991-09-06
申请人： Tetsu Tanizawa , Hideo Tokuda , Shigenori Ichinose , Katuzi Hirochi , Takehito Doi
发明人： Tetsu Tanizawa , Hideo Tokuda , Shigenori Ichinose , Katuzi Hirochi , Takehito Doi
IPC分类号： H01L21/82 , G06F17/50 , H01L23/528 , H01L27/02 , H01L23/48
CPC分类号： H01L23/5286 , G06F17/5068 , H01L27/0207 , H01L2924/0002
摘要： A semiconductor integrated circuit includes a substrate which has a predetermined width in a first direction and a predetermined length in a second direction which is approximately perpendicular to the first direction, a plurality of cells which are provided on the substrate and are grouped into a plurality of generally rectangular unit blocks, where each of the unit blocks are made up of cells having mutually different widths in the first direction but a common length in the second direction, first interconnections for supplying at least one power source voltage to the cells, where the first interconnections are provided independently for each unit block so as to supply the power source voltage in common to each of the cells making up the unit block, a row of first terminals of the cells, within each unit block, arranged in the first direction, a row of second terminals of the cells, within each unit block, arranged in the first direction an interconnection region at least including a region which is defined by the rows of the first and second terminals, and second interconnections which are provided within the interconnection region with respect to each unit block and connects the cells within the unit block.
摘要翻译：一种半导体集成电路包括：基板，其在大致垂直于第一方向的第二方向上具有在第一方向上的预定宽度和预定长度;多个单元，设置在基板上，并被分组为多个通常是矩形单位块，其中每个单位块由在第一方向上具有相互不同宽度但在第二方向上具有公共长度的单元组成，用于向单元提供至少一个电源电压的第一互连，其中第一为每个单元块独立地提供互连，以便将构成单元块的每个单元的公共电源电压提供给每个单元块中的在第一方向上布置的单元的一行第一端子，在每个单元块内的单元的第二端子排沿第一方向布置成至少包括a的互连区域区域，其由第一和第二端子的行限定，以及第二互连，其相对于每个单位块设置在互连区域内并连接单元块内的单元。

2. 发明授权

US5124776A Bipolar integrated circuit having a unit block structure 失效
标题翻译：具有单元块结构的双极集成电路
公开(公告)号：US5124776A
公开(公告)日：1992-06-23
申请号：US492898
申请日：1990-03-13
申请人： Tetsu Tanizawa , Takehito Doi , Hideo Tokuda , Shigenori Ichinose
发明人： Tetsu Tanizawa , Takehito Doi , Hideo Tokuda , Shigenori Ichinose
IPC分类号： H01L21/82 , H01L27/118
CPC分类号： H01L27/11801
摘要： A semiconductor integrated circuit comprises a plurality of first hierarchical units of logic devices each including a plurality of bipolar logic devices having a polycell structure. The bipolar logic devices have a first standardized size in a first direction and are arranged in a second direction for a second standardized size in each first hierarchical unit. Each of the first hierarchical units is defined by first and second main edges extending in the second direction for the second standardized size, and first and second side edges extending in the first direction for the first standardized size. Each of the first hierarchical units consumes a generally identical electric power and has a first power feed system extending in the second direction for the second standardized size for feeding the electric power to the bipolar logic devices therein. At least a part of the first hierarchical units are arranged in the first direction to form a plurality of second hierarchical units having respective lengths in the first direction wherein the first and second side edges are aligned in the first direction in each of the second hierarchical units. Further, the second hierarchical units are disposed such that there are at least two second hierarchical units having respective positions which are different in the second direction. Furthermore, there is provided a second power feed system extending in the first direction so as to cross the first power feed system for feeding the electric power thereto.

3. 发明授权

US07930665B2 Method and program for designing semiconductor integrated circuit 有权
标题翻译：半导体集成电路设计方法和程序
公开(公告)号：US07930665B2
公开(公告)日：2011-04-19
申请号：US11865242
申请日：2007-10-01
申请人： Shigenori Ichinose
发明人： Shigenori Ichinose
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： The method of designing a semiconductor integrated circuit of the embodiment is characterized in: reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit in a case in which a variation of a property value is not taken into consideration, and reading from a memory unit variation coefficients of the property value of the cell corresponding to a dimension of a transistor constituting the cell; and performing a static timing analysis on the semiconductor integrated circuit by using the read variation coefficients and fundamental property value.
摘要翻译：本实施例的半导体集成电路的设计方法的特征在于，在不考虑特性值的变化的情况下，从存储器单元读取构成半导体集成电路的单元的基本特性值，以及从存储单元读取与构成单元的晶体管的尺寸相对应的单元的属性值的变化系数; 以及通过使用读取的变化系数和基本特性值对半导体集成电路执行静态时序分析。

4. 发明授权

US07913212B2 Method for determining a length of shielding of a semiconductor integrated circuit wiring 有权
标题翻译：用于确定半导体集成电路布线的屏蔽长度的方法
公开(公告)号：US07913212B2
公开(公告)日：2011-03-22
申请号：US12071845
申请日：2008-02-27
申请人： Kenichi Ushiyama , Shigenori Ichinose
发明人： Kenichi Ushiyama , Shigenori Ichinose
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
摘要翻译：半导体集成电路包括屏蔽线和屏蔽线线设置的屏蔽线，并且在屏蔽线的纵向上分为多个段。

5. 发明授权

US07361975B2 Semiconductor integrated circuit having reduced cross-talk noise 有权
标题翻译：半导体集成电路具有降低的串扰噪声
公开(公告)号：US07361975B2
公开(公告)日：2008-04-22
申请号：US10914141
申请日：2004-08-10
申请人： Kenichi Ushiyama , Shigenori Ichinose
发明人： Kenichi Ushiyama , Shigenori Ichinose
IPC分类号： H01L39/00
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit, includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
摘要翻译：一种半导体集成电路，包括屏蔽线和屏蔽线线，屏蔽线线沿屏蔽线线的纵向方向分成多个段。

6. 发明授权

US06968521B2 Method, apparatus and program product for automatic placement and routing of integrated circuit 失效
标题翻译：用于集成电路自动放置和布线的方法，设备和程序产品
公开(公告)号：US06968521B2
公开(公告)日：2005-11-22
申请号：US10331513
申请日：2002-12-31
申请人： Kenichi Ushiyama , Shigenori Ichinose , Kouji Banno
发明人： Kenichi Ushiyama , Shigenori Ichinose , Kouji Banno
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5072
摘要： After automatic cell placement, the following steps are performed before performing automatic inter-cell routing. (S22) Estimated wires having Manhattan-length path are connected between same-node terminals of cells, and detected and counted is a crosstalk error that parallel-wire length is more than a predetermined value. (S23) The detected error is resolved by moving cells closely spaced less than a predetermined interval apart and connected to the error-detected estimated wires; the cell movement data is stored in a storage device; and such processes are repeated N times; and the cell placement data is modified on the basis of the cell movement data corresponding to the minimum value of error-count values of all the N times. (S24) If the minimum value is not 0, (S25) a buffer cell is inserted in the error-detected estimated wire. (S27) Obtained is the wire density of estimated wiring having Manhattan-length path, and if the density is more than a predetermined value, the design-target frame is enlarged in size, and the process returns to the automatic cell placement process.
摘要翻译：在自动单元格放置之后，在执行自动单元间路由之前执行以下步骤。（S22）具有曼哈顿长度路径的估计线路连接在小区的相同节点终端之间，并且被检测和计数是并行线长度大于预定值的串扰误差。（S23）检测到的误差通过移动细胞间隔小于预定间隔的距离并连接到检错估计的线来解决; 单元移动数据存储在存储装置中; 并且这样的处理重复N次; 并且基于与所有N次的误差计数值的最小值相对应的单元移动数据来修改单元布置数据。（S24）如果最小值不为0，则将（S25）缓冲单元插入到检测出的误差线中。（S27）获得具有曼哈顿路径的估计布线的线密度，并且如果密度大于预定值，则设计目标帧的尺寸被放大，并且处理返回到自动单元放置处理。

7. 发明申请

US20050006780A1 Semiconductor integrated circuit having reduced cross-talk noise 有权
标题翻译：半导体集成电路具有降低的串扰噪声
公开(公告)号：US20050006780A1
公开(公告)日：2005-01-13
申请号：US10914141
申请日：2004-08-10
申请人： Kenichi Ushiyama , Shigenori Ichinose
发明人： Kenichi Ushiyama , Shigenori Ichinose
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L23/522 , H01L27/04 , H01L23/52
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.
摘要翻译：半导体集成电路包括屏蔽线和屏蔽线线设置的屏蔽线，并且在屏蔽线的纵向上分为多个段。

8. 发明授权

US08584069B2 Apparatus and method for design support using layout positions of first and second terminals 有权
标题翻译：使用第一和第二终端的布局位置的设计支持的装置和方法
公开(公告)号：US08584069B2
公开(公告)日：2013-11-12
申请号：US12892481
申请日：2010-09-28
申请人： Kenichi Ushiyama , Shigenori Ichinose , Kenji Suzuki , Kenji Kumagai , Takafumi Miyahara , Shuji Tanahashi , Hideto Fukuda
发明人： Kenichi Ushiyama , Shigenori Ichinose , Kenji Suzuki , Kenji Kumagai , Takafumi Miyahara , Shuji Tanahashi , Hideto Fukuda
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.
摘要翻译：由计算机执行的设计支持方法包括：从包括布置在多个方向上的宏单元的布局数据中检测单元中的第一终端的布局位置作为第一布局位置，所述第一终端布置在第一个方向; 基于从所述第一取向到所述第二取向和所述第一布局位置的变化，计算布置在与所述第一取向不同的第二取向的第一端子的第二布局位置; 将第二布局位置与第一布局位置和布局数据相关联; 并输出关联结果。

9. 发明申请

US20050006781A1 Semiconductor integrated circuit having reduced cross-talk noise 有权
公开(公告)号：US20050006781A1
公开(公告)日：2005-01-13
申请号：US10914163
申请日：2004-08-10
申请人： Kenichi Ushiyama , Shigenori Ichinose
发明人： Kenichi Ushiyama , Shigenori Ichinose
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L23/522 , H01L27/04 , H01L23/48
CPC分类号： H01L23/5225 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

10. 发明授权

US6013924A Semiconductor integrated circuit and method for making wiring layout of semiconductor integrated circuit 失效
标题翻译：半导体集成电路及半导体集成电路布线布线方法
公开(公告)号：US6013924A
公开(公告)日：2000-01-11
申请号：US880443
申请日：1997-06-23
申请人： Toru Osajima , Noboru Yokota , Takashi Iida , Masashi Takase , Shigenori Ichinose
发明人： Toru Osajima , Noboru Yokota , Takashi Iida , Masashi Takase , Shigenori Ichinose
IPC分类号： H01L21/82 , H01L27/118
CPC分类号： H01L27/118 , H01L24/06 , H01L2224/05554 , H01L2924/14
摘要： A semiconductor integrated circuit includes a semiconductor chip; an inner cell region; a plurality of input/output cell regions which are located around the inner cell region, and a plurality of pads which are provided between the plurality of input/output regions and sides of the semiconductor chip. Each unit area of the plurality of input/output cell regions is assigned to a corresponding input/output cell so as to be just sufficient for the corresponding input/output cell.
摘要翻译：半导体集成电路包括半导体芯片; 内细胞区; 位于内单元区域周围的多个输入/输出单元区域以及设置在半导体芯片的多个输入/输出区域和侧面之间的多个焊盘。将多个输入/输出单元区域中的每个单位区域分配给相应的输入/输出单元，以便对于相应的输入/输出单元来说足够。

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