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1. 发明申请

US20140016415A1 PROGRAMMING METHOD TO TIGHTEN THRESHOLD VOLTAGE WIDTH WITH AVOIDING PROGRAM DISTURB 有权
标题翻译：使用避免程序干扰来调节阈值电压宽度的编程方法
公开(公告)号：US20140016415A1
公开(公告)日：2014-01-16
申请号：US13546553
申请日：2012-07-11
申请人： Teruhiko Kamei , Cuong Trinh , Atsushi Inoue , Toshiyuki Takahashi
发明人： Teruhiko Kamei , Cuong Trinh , Atsushi Inoue , Toshiyuki Takahashi
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/3418 , G11C16/3427
摘要： A non-volatile storage system that performs a multi-stage programming process to program non-volatile storage to a set of data threshold voltage distributions. The multi-stage programming process includes performing a first stage of the multi-stage programming process to change threshold voltages of at least a subset of the non-volatile storage elements from an erased distribution to one or more intermediate distributions, performing an intermediate stage of the multi-stage programming process to change threshold voltages of at least some of the non-volatile storage elements to appropriate distributions of the data threshold voltage distributions, and performing a later stage of the multi-stage programming process, after performing the intermediate stage of the multi-stage programming process, to tighten only a subset of the data threshold voltage distributions.
摘要翻译：执行多级编程处理以将非易失性存储器编程为一组数据阈值电压分布的非易失性存储系统。多级编程过程包括执行多阶段编程过程的第一阶段，以将非易失性存储元件的至少一个子集的阈值电压从擦除分布改变到一个或多个中间分布，执行中间阶段所述多级编程处理将所述非易失性存储元件中的至少一些的阈值电压改变为所述数据阈值电压分布的适当分布，以及在执行所述多级编程过程的后期阶段之后，执行所述多级编程处理的中间级多级编程过程，仅收紧数据阈值电压分布的子集。

2. 发明授权

US07602652B2 Systems for programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory 有权
公开(公告)号：US07602652B2
公开(公告)日：2009-10-13
申请号：US12038421
申请日：2008-02-27
申请人： Teruhiko Kamei
发明人： Teruhiko Kamei
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/3418
摘要： Non-volatile memory read operations compensate for floating gate coupling when the apparent threshold voltage of a memory cell may have shifted. A memory cell of interest can be read using a reference value based on a level of charge read from a neighboring memory cell. Misreading the neighboring cell may have greater effects in particular programming methodologies, and more specifically, when reading the neighboring cell for particular states or charge levels in those methodologies. In one embodiment, memory cells are programmed to create a wider margin between particular states where misreading a neighboring cell is more detrimental. Further, memory cells are read in one embodiment by compensating for floating gate coupling based on the state of a neighboring cell when reading at certain reference levels but not when reading at other reference levels, such as those where a wider margin has been created.

3. 发明授权

US07570520B2 Non-volatile storage system with initial programming voltage based on trial 有权
标题翻译：基于试用的初始编程电压的非易失性存储系统
公开(公告)号：US07570520B2
公开(公告)日：2009-08-04
申请号：US11616665
申请日：2006-12-27
申请人： Teruhiko Kamei , Yan Li
发明人： Teruhiko Kamei , Yan Li
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454
摘要： A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a second set of non-volatile storage elements (which may or may not include the first set).
摘要翻译：对第一组一个或多个非易失性存储元件执行试用编程过程以测试非易失性存储系统的使用。基于该试用编程，通过调整编程信号的初始幅度来校准编程信号。然后，校准的编程信号用于编程第二组非易失性存储元件（其可以包括或可以不包括第一组）。

4. 发明授权

US07440322B2 Method and system for flash memory devices 有权
标题翻译：闪存设备的方法和系统
公开(公告)号：US07440322B2
公开(公告)日：2008-10-21
申请号：US11407816
申请日：2006-04-20
申请人： Teruhiko Kamei
发明人： Teruhiko Kamei
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： Method and system for memory devices is provided. The system includes a plurality of non-volatile storage elements connected in a string between a source side element and a drain side element; a plurality of bit lines, wherein each bit line is connected to a plurality of non-volatile storage elements; and a plurality of word lines, the plurality of word lines include a dummy word line between a source side select element and a first word line that is connected to a first non-volatile storage element to be programmed, wherein a program voltage is applied to the first non-volatile storage element connected to the first word line and an intermediate voltage is applied to a second non-volatile storage element connected to the dummy word line.
摘要翻译：提供了存储器件的方法和系统。该系统包括多个在源极侧元件和漏极侧元件之间串联连接的非易失性存储元件; 多个位线，其中每个位线连接到多个非易失性存储元件; 和多条字线，所述多条字线包括源极侧选择元件与连接到要编程的第一非易失性存储元件的第一字线之间的虚拟字线，其中将程序电压施加到连接到第一字线的第一非易失性存储元件和中间电压被施加到连接到虚拟字线的第二非易失性存储元件。

5. 发明授权

US07408804B2 Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells 有权
标题翻译：用于软编程非易失性存储器的系统，其利用存储器单元的子集的单独验证和附加的软编程
公开(公告)号：US07408804B2
公开(公告)日：2008-08-05
申请号：US11296071
申请日：2005-12-06
申请人： Gerrit Jan Hemink , Teruhiko Kamei
发明人： Gerrit Jan Hemink , Teruhiko Kamei
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.
摘要翻译：一组非易失性存储元件被划分为用于软编程的子集，以便更软地编程较慢的软编程元件。整个元素组被软编程，直到被验证为软编程（或直到第一个元素子集被验证为软编程，而不是第二个子集验证）。在集合被验证为软编程之后，元素的第一子集被禁止进一步的软编程，而在第二子元素上执行附加的软编程。第二子集可以包括较慢的软编程元素。然后可以将第二个子集进行软编程验证，同时将第一个子集排除在验证之外。软编程和验证第二个子集可以继续，直到它被验证为软编程。可以使用不同的步长来增加软编程信号的大小，具体取决于软编程和验证哪个子集。

6. 发明申请

US20080158979A1 METHOD FOR PROGRAMMING WITH INITIAL PROGRAMMING VOLTAGE BASED ON TRIAL 有权
标题翻译：基于实验的初始编程电压编程方法
公开(公告)号：US20080158979A1
公开(公告)日：2008-07-03
申请号：US11616647
申请日：2006-12-27
申请人： Teruhiko Kamei , Yan Li
发明人： Teruhiko Kamei , Yan Li
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C2029/0409 , G11C2211/5621
摘要： A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a second set of non-volatile storage elements (which may or may not include the first set).
摘要翻译：对第一组一个或多个非易失性存储元件执行试用编程过程以测试非易失性存储系统的使用。基于该试用编程，通过调整编程信号的初始幅度来校准编程信号。然后，校准的编程信号用于编程第二组非易失性存储元件（其可以包括或可以不包括第一组）。

7. 发明申请

US20080127104A1 APPARATUS WITH SEGEMENTED BITSCAN FOR VERIFICATION OF PROGRAMMING 有权
标题翻译：用于验证编程的配置BITSCAN的设备
公开(公告)号：US20080127104A1
公开(公告)日：2008-05-29
申请号：US11563590
申请日：2006-11-27
申请人： Yan Li , Teruhiko Kamei , Jeffrey W. Lutze
发明人： Yan Li , Teruhiko Kamei , Jeffrey W. Lutze
IPC分类号： G06F9/44
CPC分类号： G11C16/3445 , G06F11/1072 , G11C16/344 , G11C16/3454 , G11C16/3459 , G11C29/4401 , G11C29/52 , G11C29/72 , G11C29/808
摘要： A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether to continue programming or whether the programming is successful are made based on whether overlapping groups of the non-volatile storage elements have less than a threshold number of non-volatile storage elements that are not properly programmed.
摘要翻译：一组非易失性存储元件经受编程处理以便存储一组数据。在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标条件以存储适当的数据。关于是继续编程还是编程成功的决定是基于非易失性存储元件的重叠组是否具有小于非正确编程的非易失性存储元件的阈值数量来进行。

8. 发明授权

US07352628B2 Systems for programming differently sized margins and sensing with compensations at select states for improved read operations in a non-volatile memory 有权
标题翻译：用于编程不同大小的边距和在选择状态下进行补偿的传感系统，用于改善非易失性存储器中的读取操作
公开(公告)号：US07352628B2
公开(公告)日：2008-04-01
申请号：US11425116
申请日：2006-06-19
申请人： Teruhiko Kamei
发明人： Teruhiko Kamei
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/3418
摘要： Non-volatile memory read operations compensate for floating gate coupling when the apparent threshold voltage of a memory cell may have shifted. A memory cell of interest can be read using a reference value based on a level of charge read from a neighboring memory cell. Misreading the neighboring cell may have greater effects in particular programming methodologies, and more specifically, when reading the neighboring cell for particular states or charge levels in those methodologies. In one embodiment, memory cells are programmed to create a wider margin between particular states where misreading a neighboring cell is more detrimental. Further, memory cells are read in one embodiment by compensating for floating gate coupling based on the state of a neighboring cell when reading at certain reference levels but not when reading at other reference levels, such as those where a wider margin has been created.
摘要翻译：当存储器单元的表观阈值电压可能已经偏移时，非易失性存储器读操作补偿浮栅耦合。可以使用基于从相邻存储器单元读取的电荷电平的参考值来读取感兴趣的存储器单元。对相邻小区的误读可能在特定的编程方法中具有更大的影响，更具体地说，当在这些方法中读出特定状态或电荷电平的相邻小区时。在一个实施例中，存储器单元被编程以在特定状态之间产生更宽的边界，其中对相邻单元的误读更加有害。此外，在一个实施例中，通过在某些参考电平读取时，基于相邻单元的状态补偿浮动栅极耦合，但是在其它参考电平（例如已经创建了更大的余量的其他参考电平）读取时，读取存储单元。

9. 发明授权

US06760253B2 Non-volatile semiconductor memory device and method of driving the same 失效
标题翻译：非挥发性半导体存储器件及其驱动方法
公开(公告)号：US06760253B2
公开(公告)日：2004-07-06
申请号：US10229064
申请日：2002-08-28
申请人： Teruhiko Kamei
发明人： Teruhiko Kamei
IPC分类号： G11C1600
CPC分类号： G11C7/18 , G11C16/0475 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C2211/4013
摘要： A non-volatile semiconductor memory device in which one I/O line is provided corresponding to one block region. 2N (four, for example) memory cells are provided in one block region. The adjacent memory cells are connected by a connect line. A bit line is connected to each connect line. Four bit lines are provided in one block region. The four bit lines in one block region are commonly connected to the I/O line through first select gates. A second select gate is provided between the bit line which is located at the boundary between the i-th and (i+1)th block regions which are adjacent to each other in a row direction and the I/O line corresponding to the i-th block region.
摘要翻译：一种非易失性半导体存储器件，其中对应于一个块区域提供一条I / O线。在一个块区域中提供2 （四个例如）存储器单元。相邻的存储单元通过连接线连接。一条位线连接到每个连接线。在一个块区域中提供四个位线。一个块区域中的四个位线通常通过第一选择栅极连接到I / O线。在位于行方向上彼此相邻的第i和第（i + 1）个块区域之间的边界处的位线之间提供第二选择栅极，并且与i相对应的I / O线第一块区域。

10. 发明授权

US06512698B2 Semiconductor device 有权
公开(公告)号：US06512698B2
公开(公告)日：2003-01-28
申请号：US09885859
申请日：2001-06-20
申请人： Teruhiko Kamei
发明人： Teruhiko Kamei
IPC分类号： G11C1600
CPC分类号： G11C29/12005 , G11C16/04 , G11C16/30 , G11C29/12 , G11C29/48
摘要： A semiconductor device includes a charge pump circuit 1; a voltage feeding terminal 4; a first impedance device QN3 for switching on/off an electric current path between the charge pump circuit 1 and a non-volatile memory; a second impedance device QN2 for switching on/off an electric current path between the voltage feeding terminal and the non-volatile memory; and a control circuit 5, to which a voltage is supplied from the charge pump circuit 1, for controlling the first and second impedance devices QN3 and QN2.

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