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1. 发明申请

US20100021871A1 TEACHING READING COMPREHENSION 审中-公开
标题翻译：教学阅读综合
公开(公告)号：US20100021871A1
公开(公告)日：2010-01-28
申请号：US12509387
申请日：2009-07-24
申请人： Terrence V. Layng , Victoria Ford , Marta E. Leon , Hirofumi Shimizu , Melinda S. Sota , Janet S. Twyman
发明人： Terrence V. Layng , Victoria Ford , Marta E. Leon , Hirofumi Shimizu , Melinda S. Sota , Janet S. Twyman
IPC分类号： G09B17/00
CPC分类号： G09B7/02
摘要： A creation system and method for creating routines for teaching comprehension are described. The system identifies the skill to be taught, determines one or more features for the identified skill and determines a sequence of routines based on the determined one or more features. A performance system and method for performing the determined routines are also described. The performance system identifies the skill to be taught, determines the sequence of routines for the skill and presents the sequence to the learners. The performance system also provides feedback to the learners for their responses and modifies the sequence of routines based of the learners' responses.
摘要翻译：描述了一种用于创建用于教学理解的例程的创建系统和方法。系统识别要被教导的技能，为所识别的技能确定一个或多个特征，并且基于所确定的一个或多个特征来确定例程的序列。还描述了用于执行确定的例程的性能系统和方法。表现系统识别要教授的技能，确定技能的例程顺序，并向学习者呈现序列。表现系统还向学习者提供反馈，并根据学习者的反应修改例程的顺序。

2. 发明授权

US07469367B2 Phase error determination method and digital phase-locked loop system 失效
标题翻译：相位误差确定方法和数字锁相环系统
公开(公告)号：US07469367B2
公开(公告)日：2008-12-23
申请号：US11633547
申请日：2006-12-04
申请人： Shinobu Nakamura , Mamoru Kudo , Satoru Ooshima , Jun Yamane , Hirofumi Shimizu
发明人： Shinobu Nakamura , Mamoru Kudo , Satoru Ooshima , Jun Yamane , Hirofumi Shimizu
IPC分类号： H03M13/00
CPC分类号： G11B20/1025 , G11B19/04 , G11B20/10212 , G11B20/10333 , G11B20/10425 , G11B20/1403 , G11B27/3027 , G11B2220/2562 , H03L7/107 , H03L2207/06 , H04N5/935
摘要： In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then run-length counted with a virtual channel clock so as to extract data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.
摘要翻译：在数字PLL系统中，代替使用高频时钟测量二值化的重放RF信号，通过使用N个相位时钟（例如，16个相位时钟）产生脉冲长度数据。然后用虚拟通道时钟对脉冲长度数据进行游程长度计数，以便提取数据。在该数字PLL系统中，检测在N相时钟的相邻时钟之间的间隔期间的异步信号的变化点数，以便根据检测到的变化点数确定相位误差。也可以根据与N相时钟同步的信号的变化点与N相时钟的每个时钟之间的时序关系来确定相位误差。

3. 发明申请

US20070088992A1 Phase error determination method and digital phase-locked loop system 失效
公开(公告)号：US20070088992A1
公开(公告)日：2007-04-19
申请号：US11633319
申请日：2006-12-04
申请人： Shinobu Nakamura , Mamoru Kudo , Satoru Ooshima , Jun Yamane , Hirofumi Shimizu
发明人： Shinobu Nakamura , Mamoru Kudo , Satoru Ooshima , Jun Yamane , Hirofumi Shimizu
IPC分类号： G06F11/00
CPC分类号： G11B20/1025 , G11B19/04 , G11B20/10212 , G11B20/10333 , G11B20/10425 , G11B20/1403 , G11B27/3027 , G11B2220/2562 , H03L7/107 , H03L2207/06 , H04N5/935
摘要： In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

4. 发明授权

US06848831B2 Rotation shaft support structure of a motor/generator 失效
标题翻译：电机/发电机的旋转轴支撑结构
公开(公告)号：US06848831B2
公开(公告)日：2005-02-01
申请号：US10115093
申请日：2002-04-04
申请人： Hirofumi Shimizu
发明人： Hirofumi Shimizu
IPC分类号： F16C25/06 , F16C19/54 , F16C25/08 , H02K5/173 , H02K5/24 , F16C19/08
CPC分类号： H02K5/1732 , F16C19/54 , F16C25/083 , F16C27/08 , F16C2380/26
摘要： Bearings (5, 7) fixed to the two ends of a rotation shaft (2) of a motor/generator are pressurized by plate springs 15, 17. The plate springs (15, 17) absorb the deflection off the rotation shaft (2) due to external vibration by the extension and contraction. An effective gaps L is set to value at which the bearings (5, 7) do not collide with the housing (9) in the most compressed state of the plate springs (15, 17). By this setting, the effective gap L is set to a value larger than the maximum amplitude in the direction of the rotation shaft (2) due to the external vibration.
摘要翻译：固定在马达/发电机的旋转轴（2）的两端的轴承（5,7）由板簧15,17加压。板簧（15,17）吸收旋转轴（2）的偏转，由于外部振动的延伸和收缩。将有效间隙L设定为在板簧（15,17）的最压缩状态下轴承（5,7）不与壳体（9）碰撞的值。通过该设定，由于外部振动，有效间隙L被设定为大于旋转轴（2）的方向的最大振幅的值。

5. 发明授权

US06559027B2 Semiconductor device and process for producing the sme 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06559027B2
公开(公告)日：2003-05-06
申请号：US09845338
申请日：2001-05-01
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76235 , H01L29/78
摘要： A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要翻译：一种半导体器件，其具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤，通过减小半导体上的元件隔离槽的沟槽上边缘周围的应力产生而产生从而优化元件隔离槽的形状并使器件更精细并提高器件的电气特性。

6. 发明申请

US20110309811A1 REGULATOR APPARATUS 有权
标题翻译：调节器装置
公开(公告)号：US20110309811A1
公开(公告)日：2011-12-22
申请号：US13163908
申请日：2011-06-20
申请人： Katsutoshi KONDO , Kazunori Kasuga , Hirofumi Shimizu
发明人： Katsutoshi KONDO , Kazunori Kasuga , Hirofumi Shimizu
IPC分类号： G05F1/00
CPC分类号： H02M3/1584 , H02M2001/0032 , H02M2001/325 , Y02B70/16
摘要： A regulator apparatus having an input terminal and an output terminal, the regulator apparatus includes: a plurality of regulators arranged in parallel between the input terminal and the output terminal; an conversion efficiency characteristic information obtaining unit that obtains conversion efficiency characteristic information representing a characteristic of a conversion efficiency with respect to an output current with regard to each of the plurality of regulators; a memory that stores the conversion efficiency characteristic information of each of the plurality of regulators obtained by the conversion efficiency characteristic information obtaining unit; and a switching control unit that performs a switching control on the plurality of regulators based on a value of the output current output from the output terminal and the conversion efficiency characteristic information stored in the memory.
摘要翻译：一种具有输入端子和输出端子的调节器装置，所述调节器装置包括：并联设置在所述输入端子和所述输出端子之间的多个调节器; 转换效率特性信息获取单元，获得表示关于多个调节器中的每一个的输出电流的转换效率的特性的转换效率特性信息; 存储器，其存储由所述转换效率特性信息获取单元获得的所述多个调节器中的每一个的转换效率特性信息; 以及开关控制单元，其基于从输出端子输出的输出电流的值和存储在存储器中的转换效率特性信息，对多个调节器进行开关控制。

7. 发明授权

US07653346B2 Communication terminal device, communication system, communication method, and program 失效
标题翻译：通信终端设备，通信系统，通信方法和程序
公开(公告)号：US07653346B2
公开(公告)日：2010-01-26
申请号：US11368373
申请日：2006-03-03
申请人： Jun Nishihara , Hirofumi Shimizu
发明人： Jun Nishihara , Hirofumi Shimizu
IPC分类号： H04Q7/20
CPC分类号： H04L1/1614 , H04L1/1664 , H04L1/1825 , H04L2001/0093
摘要： A communication terminal device, a communication system, a communication method, and a program which allow efficient communication processing via multicast communication, along with power saving. The communication terminal devices includes a wireless communication unit comprising: a multicast ACK generating unit which makes it possible to transmit packets having an ACK function; a multicast ACK analysis unit which analyzes received packet data for ACK information; wireless transmission and reception units which perform modulation and demodulation processing; and a central control unit and a timing control unit which control these components. The ACK function is thus implemented by multicast packets in multicast communication. This makes it possible to check if its own transmission data is received by other stations (communication terminals).
摘要翻译：一种通信终端装置，通信系统，通信方法以及通过组播通信进行有效的通信处理的节目以及节电。通信终端装置包括：无线通信单元，包括：多播ACK生成单元，其能够发送具有ACK功能的分组; 多播ACK分析单元，分析接收到的用于ACK信息的分组数据; 执行调制和解调处理的无线发送和接收单元; 以及控制这些部件的中央控制单元和定时控制单元。因此，通过组播通信中的组播数据包实现ACK功能。这使得可以检查其自己的传输数据是否被其他站（通信终端）接收。

8. 发明授权

US07342986B2 Digital PLL device 失效
标题翻译：数字PLL器件
公开(公告)号：US07342986B2
公开(公告)日：2008-03-11
申请号：US10868923
申请日：2004-06-17
申请人： Shinobu Nakamura , Mamoru Kudo , Satoru Ooshima , Jun Yamane , Hirofumi Shimizu
发明人： Shinobu Nakamura , Mamoru Kudo , Satoru Ooshima , Jun Yamane , Hirofumi Shimizu
IPC分类号： H03D3/24
CPC分类号： G11B20/10203 , G11B20/10009 , G11B20/10212 , G11B20/10222 , G11B20/10333 , G11B20/10425 , G11B20/1426 , G11B20/18 , H03L7/0807 , H03L7/0891 , H03L2207/06 , Y10S388/911
摘要： A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.
摘要翻译：锁相环装置包括时钟发生器，用于基于二值化重放信号和游程长度数据的频率产生参考时钟，并使用参考时钟产生N相时钟;脉冲长度测量装置，用于测量使用N相时钟的二值化重放信号的脉冲长度输出脉冲长度数据;以及游程长度数据提取装置，用于基于虚拟通道时钟对脉冲长度数据进行计数以提取游程长度数据。使用N相时钟（例如，16相时钟）产生脉冲长度数据。基于虚拟通道时钟对脉冲数据进行计数以提取游程长度数据。因此，不需要产生高频时钟，工作频率保持足够低。

9. 发明申请

US20070094549A1 Phase error determination method and digital phase-locked loop system 失效
标题翻译：相位误差确定方法和数字锁相环系统
公开(公告)号：US20070094549A1
公开(公告)日：2007-04-26
申请号：US11633547
申请日：2006-12-04
申请人： Shinobu Nakamura , Mamoru Kudo , Satoru Ooshima , Jun Yamane , Hirofumi Shimizu
发明人： Shinobu Nakamura , Mamoru Kudo , Satoru Ooshima , Jun Yamane , Hirofumi Shimizu
IPC分类号： G11B20/20 , G06K5/04 , G11B5/00
CPC分类号： G11B20/1025 , G11B19/04 , G11B20/10212 , G11B20/10333 , G11B20/10425 , G11B20/1403 , G11B27/3027 , G11B2220/2562 , H03L7/107 , H03L2207/06 , H04N5/935
摘要： In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.
摘要翻译：在数字PLL系统中，代替使用高频时钟测量二值化的重放RF信号，通过使用N个相位时钟（例如，16个相位时钟）产生脉冲长度数据。然后用虚拟通道时钟对脉冲长度数据进行计数，以便提取游程长度数据。在该数字PLL系统中，检测在N相时钟的相邻时钟之间的间隔期间的异步信号的变化点数，以便根据检测到的变化点数确定相位误差。也可以根据与N相时钟同步的信号的变化点与N相时钟的每个时钟之间的时序关系来确定相位误差。

10. 发明申请

US20060206783A1 Communication terminal device, communication system, communication method, and program 失效
标题翻译：通信终端设备，通信系统，通信方式和程序
公开(公告)号：US20060206783A1
公开(公告)日：2006-09-14
申请号：US11368373
申请日：2006-03-03
申请人： Jun Nishihara , Hirofumi Shimizu
发明人： Jun Nishihara , Hirofumi Shimizu
IPC分类号： H03M13/00
CPC分类号： H04L1/1614 , H04L1/1664 , H04L1/1825 , H04L2001/0093
摘要： A communication terminal device, a communication system, a communication method, and a program which allow efficient communication processing via multicast communication, along with power saving. The communication terminal devices includes a wireless communication unit comprising: a multicast ACK generating unit which makes it possible to transmit packets having an ACK function; a multicast ACK analysis unit which analyzes received packet data for ACK information; wireless transmission and reception units which perform modulation and demodulation processing; and a central control unit and a timing control unit which control these components. The ACK function is thus implemented by multicast packets in multicast communication. This makes it possible to check if its own transmission data is received by other stations (communication terminals).
摘要翻译：一种通信终端装置，通信系统，通信方法以及通过组播通信进行有效的通信处理的节目以及节电。通信终端装置包括：无线通信单元，包括：多播ACK生成单元，其能够发送具有ACK功能的分组; 多播ACK分析单元，分析接收到的用于ACK信息的分组数据; 执行调制和解调处理的无线发送和接收单元; 以及控制这些部件的中央控制单元和定时控制单元。因此，通过组播通信中的组播数据包实现ACK功能。这使得可以检查其自己的传输数据是否被其他站（通信终端）接收。

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