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1. 发明授权

US08154087B2 Multi-component strain-inducing semiconductor regions 有权
标题翻译：多组分应变诱导半导体区域
公开(公告)号：US08154087B2
公开(公告)日：2012-04-10
申请号：US13107739
申请日：2011-05-13
申请人： Ted E. Cook, Jr. , Bernhard Sell , Anand Murthy
发明人： Ted E. Cook, Jr. , Bernhard Sell , Anand Murthy
IPC分类号： H01L27/088
CPC分类号： H01L29/7848 , H01L29/66621 , H01L29/66636 , H01L29/7834
摘要： A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.
摘要翻译：描述了多组分应变诱导半导体区域。在一个实施方案中，在与晶体衬底横向相邻的这种应变诱导半导体区域的形成导致赋予晶体衬底的单轴应变，从而提供应变晶体衬底。在一个实施例中，多组分应变诱导材料区域包括由界面分离的第一部分和第二部分。在具体实施方案中，两部分的电荷 - 载流子掺杂剂杂质原子的浓度在界面处彼此不同。

2. 发明申请

US20110215375A1 MULTI-COMPONENT STRAIN-INDUCING SEMICONDUCTOR REGIONS 有权
标题翻译：多组分应变诱导半导体区域
公开(公告)号：US20110215375A1
公开(公告)日：2011-09-08
申请号：US13107739
申请日：2011-05-13
申请人： Ted E. Cook, JR. , Bernhard Sell , Anand Murthy
发明人： Ted E. Cook, JR. , Bernhard Sell , Anand Murthy
IPC分类号： H01L29/06
CPC分类号： H01L29/7848 , H01L29/66621 , H01L29/66636 , H01L29/7834
摘要： A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.
摘要翻译：描述了多组分应变诱导半导体区域。在一个实施方案中，在与晶体衬底横向相邻的这种应变诱导半导体区域的形成导致赋予晶体衬底的单轴应变，从而提供应变晶体衬底。在一个实施例中，多组分应变诱导材料区域包括由界面分离的第一部分和第二部分。在具体实施方案中，两部分的电荷 - 载流子掺杂剂杂质原子的浓度在界面处彼此不同。

3. 发明授权

US07943469B2 Multi-component strain-inducing semiconductor regions 有权
标题翻译：多组分应变诱导半导体区域
公开(公告)号：US07943469B2
公开(公告)日：2011-05-17
申请号：US11605739
申请日：2006-11-28
申请人： Ted E. Cook, Jr. , Bernhard Sell , Anand Murthy
发明人： Ted E. Cook, Jr. , Bernhard Sell , Anand Murthy
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/66621 , H01L29/66636 , H01L29/7834
摘要： A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.
摘要翻译：描述了多组分应变诱导半导体区域。在一个实施方案中，在与晶体衬底横向相邻的这种应变诱导半导体区域的形成导致赋予晶体衬底的单轴应变，从而提供应变晶体衬底。在一个实施例中，多组分应变诱导材料区域包括由界面分离的第一部分和第二部分。在具体实施方案中，两部分的电荷 - 载流子掺杂剂杂质原子的浓度在界面处彼此不同。

4. 发明申请

US20100109046A1 Methods of forming low interface resistance contacts and structures formed thereby 审中-公开
标题翻译：形成低界面电阻触点和由此形成的结构的方法
公开(公告)号：US20100109046A1
公开(公告)日：2010-05-06
申请号：US12290809
申请日：2008-11-03
申请人： Rishabh Mehandru , Bernhard Sell , Anand Murthy , Lucian Shifren
发明人： Rishabh Mehandru , Bernhard Sell , Anand Murthy , Lucian Shifren
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/28518 , H01L21/76804 , H01L21/76814 , H01L29/165 , H01L29/66628 , H01L29/66772 , H01L29/7834
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在设置在衬底上的ILD中形成锥形接触开口，其中暴露源极/漏极接触区域，对基底的源极漏极区域的一部分进行预变质，通过锥形接触开口，在源极/漏极接触区域上形成金属层，然后退火金属层以形成金属硅化物。

5. 发明申请

US20080242037A1 Semiconductor device having self-aligned epitaxial source and drain extensions 有权
标题翻译：具有自对准外延源极和漏极延伸部分的半导体器件
公开(公告)号：US20080242037A1
公开(公告)日：2008-10-02
申请号：US11729189
申请日：2007-03-28
申请人： Bernhard Sell , Tahir Ghani , Anand Murthy , Harry Gomez
发明人： Bernhard Sell , Tahir Ghani , Anand Murthy , Harry Gomez
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.
摘要翻译：一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底区域中，其中掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料基质。

6. 发明申请

US20070238236A1 Structure and fabrication method of a selectively deposited capping layer on an epitaxially grown source drain 审中-公开
标题翻译：在外延生长的源极漏极上的选择性沉积的覆盖层的结构和制造方法
公开(公告)号：US20070238236A1
公开(公告)日：2007-10-11
申请号：US11391928
申请日：2006-03-28
申请人： Ted Cook , Bernhard Sell , Anand Murthy
发明人： Ted Cook , Bernhard Sell , Anand Murthy
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method and apparatus to improve the contact formation of salicide and reduce the external resistance of a transistor is disclosed. A gate electrode is formed on a surface of a substrate. A source region and a drain region are isotropically etched in the substrate. A Silicon Germanium alloy is doped in situ with Boron in the source region and in the drain region. Silicon is deposited on the Silicon Germanium alloy. Nickel is deposited on the Silicon. A Nickel Silicon Germanium silicide layer is formed on the Silicon Germanium alloy. A Nickel Silicon silicide layer is formed on the Nickel Silicon Germanium silicide layer.
摘要翻译：公开了一种改善硅化物的接触形成并降低晶体管的外部电阻的方法和装置。在基板的表面上形成栅电极。源极区域和漏极区域在基板中被各向同性地蚀刻。在源区和漏区中硼原位掺杂硅锗合金。硅沉积在硅锗合金上。镍沉积在硅上。在硅锗合金上形成硅锗硅化硅层。镍硅化硅层形成在硅锗硅化硅层上。

7. 发明申请

US20090321838A1 CMOS DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US20090321838A1
公开(公告)日：2009-12-31
申请号：US12215989
申请日：2008-06-30
申请人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel B. Aubertine
发明人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel B. Aubertine
IPC分类号： H01L29/423 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823835 , H01L29/66628 , H01L29/7834
摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.
摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134）绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

8. 发明授权

US07663192B2 CMOS device and method of manufacturing same 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US07663192B2
公开(公告)日：2010-02-16
申请号：US12215989
申请日：2008-06-30
申请人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel Aubertine
发明人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel Aubertine
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823835 , H01L29/66628 , H01L29/7834
摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.
摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134）绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

9. 发明申请

US20120068180A1 METHODS OF FORMING LOW INTERFACE RESISTANCE CONTACTS AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成低界面电阻接触和结构的方法
公开(公告)号：US20120068180A1
公开(公告)日：2012-03-22
申请号：US13292865
申请日：2011-11-09
申请人： Rishabh Mehandru , Bernhard Sell , Anand Murthy , Lucian Shifren
发明人： Rishabh Mehandru , Bernhard Sell , Anand Murthy , Lucian Shifren
IPC分类号： H01L29/78
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/28518 , H01L21/76804 , H01L21/76814 , H01L29/165 , H01L29/66628 , H01L29/66772 , H01L29/7834
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在设置在衬底上的ILD中形成锥形接触开口，其中暴露源极/漏极接触区域，对基底的源极漏极区域的一部分进行预变质，通过锥形接触开口，在源极/漏极接触区域上形成金属层，然后退火金属层以形成金属硅化物。

10. 发明授权

US07732285B2 Semiconductor device having self-aligned epitaxial source and drain extensions 有权
标题翻译：具有自对准外延源极和漏极延伸部分的半导体器件
公开(公告)号：US07732285B2
公开(公告)日：2010-06-08
申请号：US11729189
申请日：2007-03-28
申请人： Bernhard Sell , Tahir Ghani , Anand Murthy , Harry Gomez
发明人： Bernhard Sell , Tahir Ghani , Anand Murthy , Harry Gomez
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.
摘要翻译：一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底区域中，其中掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料基质。

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