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1. 发明申请

US20140284626A1 ENHANCED DISLOCATION STRESS TRANSISTOR 审中-公开
标题翻译：增强分离应力晶体管
公开(公告)号：US20140284626A1
公开(公告)日：2014-09-25
申请号：US14297847
申请日：2014-06-06
申请人： Cory Weber , Mark Liu , Anand Murthy , Hemant Deshpande , Daniel B. Aubertine
发明人： Cory Weber , Mark Liu , Anand Murthy , Hemant Deshpande , Daniel B. Aubertine
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/7848 , H01L21/26506 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/66477 , H01L29/66628 , H01L29/78 , H01L29/7847 , H01L29/7849
摘要： A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
摘要翻译：提供了一种设备。该器件包括形成在半导体衬底上的晶体管，该晶体管具有导通通道。该器件包括与半导体衬底上的导电沟道相邻形成的至少一个边缘位错。该装置还包括在导电通道之上引入的至少一个自由表面和至少一个边缘错位。

2. 发明授权

US08779477B2 Enhanced dislocation stress transistor 有权
标题翻译：增强位错应力晶体管
公开(公告)号：US08779477B2
公开(公告)日：2014-07-15
申请号：US12191814
申请日：2008-08-14
申请人： Cory Weber , Mark Liu , Anand Murthy , Hemant Deshpande , Daniel B. Aubertine
发明人： Cory Weber , Mark Liu , Anand Murthy , Hemant Deshpande , Daniel B. Aubertine
IPC分类号： H01L29/76
CPC分类号： H01L29/7848 , H01L21/26506 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/66477 , H01L29/66628 , H01L29/78 , H01L29/7847 , H01L29/7849
摘要： A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
摘要翻译：提供了一种设备。该器件包括形成在半导体衬底上的晶体管，该晶体管具有导通沟道。该器件包括与半导体衬底上的导电沟道相邻形成的至少一个边缘位错。该装置还包括在导电通道之上引入的至少一个自由表面和至少一个边缘错位。

3. 发明申请

US20100042508A1 Method and Apparatus for Implementing a Peer to Peer Transaction System 审中-公开
标题翻译：实现对等交易系统的方法和装置
公开(公告)号：US20100042508A1
公开(公告)日：2010-02-18
申请号：US12191994
申请日：2008-08-14
申请人： Reza Bundy , John Shiple , Mark Liu
发明人： Reza Bundy , John Shiple , Mark Liu
IPC分类号： G06Q30/00 , G06Q50/00
CPC分类号： G06Q30/00 , G06Q30/0283 , G06Q30/0601
摘要： The system provides a method an apparatus for implementing a peer to peer transaction system. The system includes an online system of marketing and pricing that optimizes saleability and profit, limits access of strangers to personal spaces, limits the likelihood of unqualified buyers, provides appropriate paperwork automatically, and reduces the cycle time of offer and sale. The system also provides trustworthy information to a buyer of physical condition and title, as well as resources normally only available in a commercial transaction.
摘要翻译：该系统提供了一种用于实现对等交易系统的装置的方法。该系统包括市场营销和定价在线系统，优化销售和利润，限制陌生人到个人空间的访问，限制不合格买家的可能性，自动提供适当的文书工作，并减少报价和销售的周期时间。该系统还向买方提供可靠的信息给物理条件和标题，以及通常仅在商业交易中可用的资源。

4. 发明申请

US20090321838A1 CMOS DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US20090321838A1
公开(公告)日：2009-12-31
申请号：US12215989
申请日：2008-06-30
申请人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel B. Aubertine
发明人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel B. Aubertine
IPC分类号： H01L29/423 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823835 , H01L29/66628 , H01L29/7834
摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.
摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134）绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

5. 发明申请

US20070224785A1 Strain-inducing film formation by liquid-phase epitaxial re-growth 审中-公开
标题翻译：通过液相外延再生长的应变诱导膜形成
公开(公告)号：US20070224785A1
公开(公告)日：2007-09-27
申请号：US11386518
申请日：2006-03-21
申请人： Mark Liu
发明人： Mark Liu
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02667 , H01L21/02381 , H01L21/2022 , H01L21/2026 , H01L21/26506 , H01L21/268 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method to form a strain-inducing three-component epitaxial film is described. In an embodiment, a three-component epitaxial film comprises atoms from a parent film, charge-neutral lattice-substitution impurities and charge carrier dopant impurities. In one embodiment, the charge-neutral lattice-substitution impurities are smaller and present in greater concentration than the charge carrier dopant impurities.
摘要翻译：描述形成应变诱导三组分外延膜的方法。在一个实施例中，三组分外延膜包含来自母膜的电子 - 电荷 - 中性晶格取代杂质和电荷载体掺杂剂杂质的原子。在一个实施方案中，电荷 - 中性晶格取代杂质更小并且以比载电子掺杂剂杂质更高的浓度存在。

6. 发明申请

US20050224980A1 Interconnect adapted for reduced electron scattering 审中-公开
标题翻译：互连适用于减少电子散射
公开(公告)号：US20050224980A1
公开(公告)日：2005-10-13
申请号：US10816470
申请日：2004-03-31
申请人： Jihperng Leu , Chih-I Wu , Mark Liu , Kevin Fischer , Chia-Hong Jan , David Gracias
发明人： Jihperng Leu , Chih-I Wu , Mark Liu , Kevin Fischer , Chia-Hong Jan , David Gracias
IPC分类号： H01L21/288 , H01L21/44 , H01L21/768
CPC分类号： H01L21/2885 , H01L21/76888
摘要： A die is provided with an interconnect, and the grain structure of the interconnect is adapted to reduce electron scattering.
摘要翻译：模具设置有互连，并且互连的晶粒结构适于减少电子散射。

7. 发明申请

US20050191857A1 Capping layer for a semiconductor device and a method of fabrication 审中-公开
标题翻译：用于半导体器件的封盖层和制造方法
公开(公告)号：US20050191857A1
公开(公告)日：2005-09-01
申请号：US11014081
申请日：2004-12-15
申请人： Mark Liu
发明人： Mark Liu
IPC分类号： H01L21/268 , H01L21/302 , H01L21/336 , H01L21/461
CPC分类号： H01L21/268 , H01L29/6659
摘要： Numerous embodiments of a method and apparatus for a capping layer are disclosed. In one embodiment, a method of forming a capping layer for a semiconductor device comprises forming one or more layers on at least a portion of the top surface of a semiconductor device, substantially planarizing at least one of the one or more layers, annealing at least a portion of the semiconductor device, and removing a substantial portion of the one or more layers, using one or more etching processes.
摘要翻译：公开了一种用于封盖层的方法和装置的许多实施例。在一个实施例中，形成用于半导体器件的覆盖层的方法包括在半导体器件的顶表面的至少一部分上形成一个或多个层，基本平坦化至少一个或多个层，至少退火半导体器件的一部分，并且使用一个或多个蚀刻工艺去除所述一个或多个层的大部分。

8. 发明申请

US20050145893A1 Methods for fabricating metal gate structures 审中-公开
标题翻译：制造金属门结构的方法
公开(公告)号：US20050145893A1
公开(公告)日：2005-07-07
申请号：US10748345
申请日：2003-12-29
申请人： Mark Doczy , Mark Liu , Jack Kavalieros , Justin Brask , Matthew Metz , Robert Chau
发明人： Mark Doczy , Mark Liu , Jack Kavalieros , Justin Brask , Matthew Metz , Robert Chau
IPC分类号： H01L21/268 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/8234 , H01L29/76 , H01L31/062
CPC分类号： H01L29/495 , H01L21/268 , H01L21/823828 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66575 , H01L29/6659
摘要： Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.
摘要翻译：描述形成微电子结构的方法。这些方法包括提供包括源极/漏极和栅极区域的衬底，其中栅极区域包括设置在栅极介电层上的金属层，然后激光退火衬底。

9. 发明授权

US07663192B2 CMOS device and method of manufacturing same 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US07663192B2
公开(公告)日：2010-02-16
申请号：US12215989
申请日：2008-06-30
申请人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel Aubertine
发明人： Bernhard Sell , Anand Murthy , Mark Liu , Daniel Aubertine
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823835 , H01L29/66628 , H01L29/7834
摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.
摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134）绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

10. 发明申请

US20090268229A1 Multifunction Peripheral Browser Control for Application Integration 审中-公开
标题翻译：用于应用集成的多功能外设浏览器控件
公开(公告)号：US20090268229A1
公开(公告)日：2009-10-29
申请号：US12107926
申请日：2008-04-23
申请人： TANNA MARIE RICHARDSON , MARK LIU STEVENS , JOEY PHILIP LUM
发明人： TANNA MARIE RICHARDSON , MARK LIU STEVENS , JOEY PHILIP LUM
IPC分类号： G06K15/00
CPC分类号： G06K15/00 , G03G15/5087 , G03G2215/00109 , G06K15/005
摘要： A multi-functional peripheral (MFP) browser having integrated scan, print, and/or e-mail functionality may be integrated within a system and support methods of scanning, printing and e-mailing via the MFP display.
摘要翻译：具有集成扫描，打印和/或电子邮件功能的多功能外围设备（MFP）浏览器可以集成在系统内，并支持通过MFP显示器的扫描，打印和电子邮件的方法。

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