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1. 发明授权

US6046605A Bidirectional asynchronous open collector buffer 失效
标题翻译：双向异步开放收集器缓冲区
公开(公告)号：US6046605A
公开(公告)日：2000-04-04
申请号：US934279
申请日：1997-09-19
申请人： Ted B. Ziemkowski , Gregory A. Hill , Daniel E. Yee
发明人： Ted B. Ziemkowski , Gregory A. Hill , Daniel E. Yee
IPC分类号： H03K19/0175
CPC分类号： H03K19/01759
摘要： A bidirectional asynchronous open collector buffer. The buffer employs set delays and control logic to prevent latch up of the buffer when the low signal is applied to one of the ports of the buffer. Additionally, the buffer employs reset delays in conjunction with the control logic for suppressing oscillation of the buffer when one of the ports of the buffer is released from the applied low signal.
摘要翻译：双向异步开放收集器缓冲区。当低信号被施加到缓冲器的一个端口时，缓冲器采用设置延迟和控制逻辑来防止缓冲器锁存。此外，当缓冲器的一个端口从施加的低信号中解除时，缓冲器结合用于抑制缓冲器的振荡的控制逻辑使用复位延迟。

2. 发明授权

US5802565A Speed optimal bit ordering in a cache memory 失效
标题翻译：在缓存中调速最佳位排序
公开(公告)号：US5802565A
公开(公告)日：1998-09-01
申请号：US705443
申请日：1996-08-29
申请人： John G. McBride , Ted B. Ziemkowski
发明人： John G. McBride , Ted B. Ziemkowski
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0895
摘要： Disclosed herein are methods and apparatus relating to speed optimal bit ordering in a cache memory. All of the data arrays capable of driving a single output bit are grouped with combinational I/O logic for driving same. The data arrays and combinational I/O logic corresponding to a single output bit can be thought of as a bit slice of a cache. Bit slices are preferably arranged so that predecode bit slices are nearest to the I/O end of the cache. A number of predecode bit slices corresponding to a single instruction or data word are preferably followed by the instruction's predecode data bit slices. Non-predecode data bit slices are arranged so that big/little endien data bit pairs are adjacent to one another, or as close to each other as possible given other bit slice ordering restraints. The arrangement of bit slices in big/little endien pairs yields I/O buses of minimum length. Components of combinational I/O logic are arranged in staggered form, perpendicularly to the I/O datapath of a cache. In this manner, a single control line can latch all of the elements in a logical register.
摘要翻译：这里公开了与高速缓冲存储器中的速度最佳比特排序有关的方法和装置。能够驱动单个输出位的所有数据阵列都以组合I / O逻辑进行分组，以驱动它们。对应于单个输出位的数据阵列和组合I / O逻辑可以被认为是缓存的位片。位片优选地被布置成使得预代码位片最接近高速缓存的I / O端。对应于单个指令或数据字的多个预解码比特片优选地跟随指令的预代码数据比特片段。非预解码数据位片被布置成使得大/小的内部数据位对彼此相邻，或者尽可能靠近彼此，给定其他位片排序约束。大/小端对中的位片的排列产生最小长度的I / O总线。组合I / O逻辑的组件以垂直于缓存的I / O数据路径的交错格式布置。以这种方式，单个控制线可以锁存逻辑寄存器中的所有元件。

3. 发明授权

US6031709A Switching multiplexor arrangement of relays for balancing thermal offset 失效
标题翻译：用于平衡热偏移的继电器的开关多路复用器布置
公开(公告)号：US6031709A
公开(公告)日：2000-02-29
申请号：US118951
申请日：1998-07-17
申请人： Ted B. Ziemkowski
发明人： Ted B. Ziemkowski
IPC分类号： H01H67/24 , H01H51/28
CPC分类号： H01H67/24 , Y10T307/76
摘要： A switching multiplexor arrangement of relays having configuration flexibility and operative for balancing thermal offset of the relays Accumulated thermal offset of the relays along the various propagation paths through the multiplexor is balanced, by maintaining equal numbers of configured relays, along the various propagation paths, so that there are substantially equal amounts of accumulated thermal offset for the various propagation paths.
摘要翻译：具有配置灵活性并且用于平衡继电器的热偏移的继电器的开关多路复用器装置通过沿着各种传播路径维持相等数量的配置的继电器来平衡通过多路复用器的沿着各种传播路径的继电器的累积热偏移，因此对于各种传播路径存在基本相等量的累积热偏移。

4. 发明授权

US5854943A Speed efficient cache output selector circuitry based on tag compare and data organization 失效
标题翻译：基于标签比较和数据组织的高速缓存输出选择器电路
公开(公告)号：US5854943A
公开(公告)日：1998-12-29
申请号：US689173
申请日：1996-08-07
申请人： John G. McBride , Ted B. Ziemkowski
发明人： John G. McBride , Ted B. Ziemkowski
IPC分类号： G06F12/08 , G06F15/02
CPC分类号： G06F12/0864 , G06F12/0886
摘要： A cache output selector for a multi-way set-associative cache memory which provides for simultaneous access of multiple-word data is presented. The cache memory comprises a plurality of data arrays wherein no two consecutive multiple-word reside in the same data. The cache output selector of the present invention includes, for each data array of the plurality of data arrays, a qualifying multiplexor which receives the respective tag match signals from each of the tag matching circuits as data input and a set selector signal, as selector input, and at least one qualifying signal as qualifying input. The set selector signal indicates which data array a first set of the multi-way set-associative memory resides in during a current read/write cycle. The qualifying multiplexor combines a clock qualifying functionality and a multiplexor functionality to produce a data array output enable signal in only two levels of logic. The cache memory comprises a prefetch buffer path and a bypass path from which the cache output selector selects an addressed multi-word for output. The output path selected circuit includes a pair of qualifying NOR gates. Each qualifying NOR gate combines a clock qualifying functionality and a logical NOR functionality to produce a qualified prefetch buffer path output enable signal and a qualified bypass path output enable signal respectively.
摘要翻译：提出了一种用于多路组合相关高速缓冲存储器的高速缓存输出选择器，其提供多字数据的同时访问。高速缓冲存储器包括多个数据阵列，其中没有两个连续的多字存在于同一数据中。本发明的高速缓存输出选择器对于多个数据阵列的每个数据阵列包括一个合格的多路复用器，它接收来自每个标签匹配电路的各个标签匹配信号作为数据输入和一个设置选择器信号作为选择器输入，以及至少一个合格信号作为合格输入。设置选择器信号指示在当前读/写周期期间多路组合关联存储器的第一组的哪个数据阵列。合格多路复用器组合了时钟限定功能和多路复用器功能，以仅在两个逻辑层级产生数据阵列输出使能信号。高速缓存存储器包括预取缓冲器路径和旁路路径，高速缓存输出选择器从该路径选择所寻址的多字以输出。输出路径选择电路包括一对合格的或非门。每个合格的NOR门组合了时钟限定功能和逻辑NOR功能，以分别产生合格的预取缓冲器路径输出使能信号和合格的旁路路径输出使能信号。

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