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1. 发明授权

US5802565A Speed optimal bit ordering in a cache memory 失效
标题翻译：在缓存中调速最佳位排序
公开(公告)号：US5802565A
公开(公告)日：1998-09-01
申请号：US705443
申请日：1996-08-29
申请人： John G. McBride , Ted B. Ziemkowski
发明人： John G. McBride , Ted B. Ziemkowski
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0895
摘要： Disclosed herein are methods and apparatus relating to speed optimal bit ordering in a cache memory. All of the data arrays capable of driving a single output bit are grouped with combinational I/O logic for driving same. The data arrays and combinational I/O logic corresponding to a single output bit can be thought of as a bit slice of a cache. Bit slices are preferably arranged so that predecode bit slices are nearest to the I/O end of the cache. A number of predecode bit slices corresponding to a single instruction or data word are preferably followed by the instruction's predecode data bit slices. Non-predecode data bit slices are arranged so that big/little endien data bit pairs are adjacent to one another, or as close to each other as possible given other bit slice ordering restraints. The arrangement of bit slices in big/little endien pairs yields I/O buses of minimum length. Components of combinational I/O logic are arranged in staggered form, perpendicularly to the I/O datapath of a cache. In this manner, a single control line can latch all of the elements in a logical register.
摘要翻译：这里公开了与高速缓冲存储器中的速度最佳比特排序有关的方法和装置。能够驱动单个输出位的所有数据阵列都以组合I / O逻辑进行分组，以驱动它们。对应于单个输出位的数据阵列和组合I / O逻辑可以被认为是缓存的位片。位片优选地被布置成使得预代码位片最接近高速缓存的I / O端。对应于单个指令或数据字的多个预解码比特片优选地跟随指令的预代码数据比特片段。非预解码数据位片被布置成使得大/小的内部数据位对彼此相邻，或者尽可能靠近彼此，给定其他位片排序约束。大/小端对中的位片的排列产生最小长度的I / O总线。组合I / O逻辑的组件以垂直于缓存的I / O数据路径的交错格式布置。以这种方式，单个控制线可以锁存逻辑寄存器中的所有元件。

2. 发明授权

US5854943A Speed efficient cache output selector circuitry based on tag compare and data organization 失效
标题翻译：基于标签比较和数据组织的高速缓存输出选择器电路
公开(公告)号：US5854943A
公开(公告)日：1998-12-29
申请号：US689173
申请日：1996-08-07
申请人： John G. McBride , Ted B. Ziemkowski
发明人： John G. McBride , Ted B. Ziemkowski
IPC分类号： G06F12/08 , G06F15/02
CPC分类号： G06F12/0864 , G06F12/0886
摘要： A cache output selector for a multi-way set-associative cache memory which provides for simultaneous access of multiple-word data is presented. The cache memory comprises a plurality of data arrays wherein no two consecutive multiple-word reside in the same data. The cache output selector of the present invention includes, for each data array of the plurality of data arrays, a qualifying multiplexor which receives the respective tag match signals from each of the tag matching circuits as data input and a set selector signal, as selector input, and at least one qualifying signal as qualifying input. The set selector signal indicates which data array a first set of the multi-way set-associative memory resides in during a current read/write cycle. The qualifying multiplexor combines a clock qualifying functionality and a multiplexor functionality to produce a data array output enable signal in only two levels of logic. The cache memory comprises a prefetch buffer path and a bypass path from which the cache output selector selects an addressed multi-word for output. The output path selected circuit includes a pair of qualifying NOR gates. Each qualifying NOR gate combines a clock qualifying functionality and a logical NOR functionality to produce a qualified prefetch buffer path output enable signal and a qualified bypass path output enable signal respectively.
摘要翻译：提出了一种用于多路组合相关高速缓冲存储器的高速缓存输出选择器，其提供多字数据的同时访问。高速缓冲存储器包括多个数据阵列，其中没有两个连续的多字存在于同一数据中。本发明的高速缓存输出选择器对于多个数据阵列的每个数据阵列包括一个合格的多路复用器，它接收来自每个标签匹配电路的各个标签匹配信号作为数据输入和一个设置选择器信号作为选择器输入，以及至少一个合格信号作为合格输入。设置选择器信号指示在当前读/写周期期间多路组合关联存储器的第一组的哪个数据阵列。合格多路复用器组合了时钟限定功能和多路复用器功能，以仅在两个逻辑层级产生数据阵列输出使能信号。高速缓存存储器包括预取缓冲器路径和旁路路径，高速缓存输出选择器从该路径选择所寻址的多字以输出。输出路径选择电路包括一对合格的或非门。每个合格的NOR门组合了时钟限定功能和逻辑NOR功能，以分别产生合格的预取缓冲器路径输出使能信号和合格的旁路路径输出使能信号。

3. 发明授权

US5471640A Programmable disk array controller having n counters for n disk drives for stripping data where each counter addresses specific memory location by a count n 失效
标题翻译：可编程磁盘阵列控制器，具有n个磁盘驱动器的n个计数器，用于剥离数据，其中每个计数器以特定的存储位置寻址计数n
公开(公告)号：US5471640A
公开(公告)日：1995-11-28
申请号：US909902
申请日：1992-07-06
申请人： John G. McBride
发明人： John G. McBride
IPC分类号： G06F3/06 , G06F11/10 , G06F13/10 , G11C29/00 , H01J3/00
CPC分类号： G11C29/88 , G06F3/0601 , G06F11/1008 , G06F2003/0691
摘要： A programmable disk array controller distributes contiguous data from a host processor across a plurality of disk drives. The controller includes a device port with a plurality of connected disk drives. A dual ported buffer memory receives data from the host processor for storage to the disk drives. The programmable controller accesses data from the buffer memory and causes it to be fed to the device port for storage in the disk drives. The programmable controller includes a variable increment counter associated with each disk drive for controlling the data address accessed from the buffer memory. Each variable increment counter is programmable to sequentially increment a count by a value n so that its associated disk drive receives every nth data segment from the buffer memory.
摘要翻译：可编程磁盘阵列控制器通过多个磁盘驱动器分配来自主机处理器的连续数据。控制器包括具有多个连接的磁盘驱动器的设备端口。双端口缓冲存储器从主机处理器接收数据以存储到磁盘驱动器。可编程控制器从缓冲存储器访问数据，并将其送入设备端口以存储在磁盘驱动器中。可编程控制器包括与每个磁盘驱动器相关联的可变增量计数器，用于控制从缓冲存储器访问的数据地址。每个可变增量计数器是可编程的，以使计数依次递增值n，使得其相关的磁盘驱动器从缓冲存储器接收每第n个数据段。

4. 发明授权

US5987237A Framework for rules checking 失效
标题翻译：规则检查框架
公开(公告)号：US5987237A
公开(公告)日：1999-11-16
申请号：US922793
申请日：1997-09-02
申请人： John G. McBride
发明人： John G. McBride
IPC分类号： G01R31/00 , G06F17/10 , G06F17/50 , G06F9/455
CPC分类号： G06F17/5036 , G06F17/5022
摘要： A rules checking methodology ensures the quality of a structure or system having one or more elements and one or more nodes that serve as connection points to the elements. The rules checking methodology examines the elements and nodes of the structure and makes decisions regarding the quality of the structure according to parameters, or rules, provided.
摘要翻译：规则检查方法确保具有一个或多个元素的结构或系统的质量，以及用作元素的连接点的一个或多个节点。规则检查方法检查结构的要素和结点，并根据提供的参数或规则对结构的质量进行决策。

5. 发明授权

US5765194A Timing consistent dynamic compare with force miss circuit 失效
标题翻译：与力漏电路相比，时序一致动态
公开(公告)号：US5765194A
公开(公告)日：1998-06-09
申请号：US641655
申请日：1996-05-01
申请人： John G. McBride
发明人： John G. McBride
IPC分类号： G06F12/08 , G06F9/28 , G06F9/26
CPC分类号： G06F12/0888
摘要： A dynamic tag match circuit (10) has exclusive-OR gates (18) each of which receives one bit of an address signal (A) from cache tag RAM, an inverted bit of the address signal (NA) from the cache tag RAM, and one bit of an address signal (B) from an address translator. The exclusive-OR gates (18) are in parallel to each other and output a hit signal which is low only when a match occurs between the two address signals. Additionally, the hit signal is low only when the results of a force miss circuit (14) indicate that a force miss should not occur. The dynamic tag match circuit (10) further has a pull-up circuit (16) for precharging the output of the circuit (16) and for holding the output of the circuit (16) at one of the two logical levels. The force miss circuit (14) advantageously incorporates logic which coordinates the timing of the force miss evaluation with the arrival of the address (A) from the cache tag RAM. As a result, the timing of the circuit (10) is consistent regardless of where a miss originates, whether it be from the address compare circuit (12) or the force miss circuit (14). The consistency in timing simplifies the evaluation and characterization of any chip or circuit incorporating the dynamic compare circuit (10), increases the overall speed of the circuit (10), and simplifies the design of the circuits generating the force miss input signals as well as circuits downstream of the tag match circuit (10).
摘要翻译：动态标签匹配电路（10）具有异或门（18），每个门从高速缓存标签RAM接收地址信号（A）的一位，来自高速缓存标签RAM的地址信号（NA）的反相位，和来自地址转换器的一位地址信号（B）。异或门（18）彼此并联，并且仅当两个地址信号之间发生匹配时输出低电平的命中信号。此外，只有当力缺失电路（14）的结果指示不会发生力缺失时，命中信号才为低。动态标签匹配电路（10）还具有用于对电路（16）的输出进行预充电并将电路（16）的输出保持在两个逻辑电平中的一个上的上拉电路（16）。力缺失电路（14）有利地结合了逻辑，该逻辑协调了力错过评估的定时与来自高速缓存标签RAM的地址（A）的到达。结果，无论来自地址比较电路（12）还是力缺失电路（14），电路（10）的定时都是一致的。时序的一致性简化了包含动态比较电路（10）的任何芯片或电路的评估和表征，增加了电路（10）的整体速度，并且简化了产生力未知输入信号的电路的设计，以及在标签匹配电路（10）的下游的电路。

6. 发明授权

US06487703B1 Method and system for screening a VLSI design for inductive coupling noise 失效
标题翻译：用于筛选感应耦合噪声的VLSI设计的方法和系统
公开(公告)号：US06487703B1
公开(公告)日：2002-11-26
申请号：US09909297
申请日：2001-07-19
申请人： John G. McBride , Osamn S. Nakagawa , Shen Lin
发明人： John G. McBride , Osamn S. Nakagawa , Shen Lin
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method is disclosed for estimating inductive coupling noise of a signal on a transmission line in a circuit design stored in a computer memory. The method determines the capacitive coupling noise on the signal, adds inductive coupling noise, and compares the total to a specified maximum amount of noise. The inductive coupling is a percentage of a supply voltage, which percentage varies depending upon the transition rate of the signal, the resistance of the line, and the gate capacitance of a load on the line. The inductive coupling varies based on the circuit design and may be stored in a table having inductive coupling values for multiple design conditions. The table is created using a field solver to determine line characteristics and a circuit simulator to simulate inductive coupling noise. For each set of initial conditions, a worst-case inductive coupling value is recorded in the table.
摘要翻译：公开了一种用于估计存储在计算机存储器中的电路设计中的传输线上的信号的感应耦合噪声的方法。该方法确定信号上的电容耦合噪声，增加电感耦合噪声，并将总和与指定的最大噪声量进行比较。电感耦合是电源电压的百分比，该百分比取决于信号的转换速率，线路的电阻和线路上的负载的栅极电容。电感耦合基于电路设计而变化，并且可以存储在具有多个设计条件的感应耦合值的表中。该表使用场求解器创建以确定线路特性，并使用电路仿真器来模拟电感耦合噪声。对于每组初始条件，最坏情况的电感耦合值记录在表中。

7. 发明授权

US06367062B1 System and method for detecting an excessive number of series-connected pass FETs 失效
标题翻译：用于检测过多串联连接的FET的系统和方法
公开(公告)号：US06367062B1
公开(公告)日：2002-04-02
申请号：US09252138
申请日：1999-02-18
申请人： John G. McBride
发明人： John G. McBride
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： In accordance with one aspect of the invention, a method is provided for identifying multiple, series-connected pass FETs in an integrated circuit, by evaluating a current node in the netlist to determine whether the current node is a static gate input (or output). If the node is that of a pass gate input (or output), the method then identifies at least one pass FET that is channel-connected to the current node, and determines that an output node (input node) of the at least one pass FET is the same node as the current node. Thereafter, the method reassigns the current node to be an input node (output node) of the at least one pass FET, and repeats the foregoing steps (beginning with identifying at least one pass FET that is channel-connected to the current node). In accordance with another aspect of the present invention, a system is provided for identifying multiple, series-connected pass FETs in an integrated circuit by evaluating a netlist. Preferably, the system is implemented in software and includes various code segments for: identifying a current node that is at an endpoint of a series of pass FET devices, identifying at least one pass FET that is series connected to the current node, evaluating direction of the at least one pass FET device, and resetting a new “current node” to a channel node of the at least one pass FET that is opposite the previous “current node”.
摘要翻译：根据本发明的一个方面，提供了一种通过评估网表中的当前节点来确定当前节点是静态门输入（或输出）的方法，用于在集成电路中识别多个串联连接的通过FET，。如果节点是传递门输入（或输出）的节点，则该方法然后识别至少一个通道连接到当前节点的通过FET，并确定至少一个通过的输出节点（输入节点） FET与当前节点相同。此后，该方法将当前节点重新分配为至少一个通过FET的输入节点（输出节点），并且重复上述步骤（从识别至少一个通道连接到当前节点的通过FET开始）。根据本发明的另一方面，提供一种通过评估网表来识别集成电路中的多个串联连接的FET的系统。优选地，该系统以软件实现，并且包括各种代码段，用于：识别位于一系列通过FET器件的端点处的当前节点，识别串联连接到当前节点的至少一个通过FET，评估方向所述至少一个通过FET器件，并且将新的“当前节点”复位到与先前的“当前节点”相对的至少一个通过FET的通道节点。

8. 发明授权

US5689634A Three purpose shadow register attached to the output of storage devices 失效
标题翻译：三个目的影子寄存器连接到存储设备的输出
公开(公告)号：US5689634A
公开(公告)日：1997-11-18
申请号：US717646
申请日：1996-09-23
申请人： John G. McBride
发明人： John G. McBride
IPC分类号： G06F11/22 , G11C29/48 , H04B17/00
CPC分类号： G11C29/48 , G06F11/22
摘要： A multi-purpose shadow register apparatus in a computer system having a central processing unit, a memory, a memory output select circuit, and a memory output bus includes a shadow register in parallel with the memory output select circuit. The shadow register is connected to receive memory output data from the memory output bus and is responsive to an output enable signal to provide shadow register output data on a shadow register output bus. A shadow register functional logic block which provides a plurality of functional blocks utilize the shadow register in a mutually time-exclusive manner.
摘要翻译：具有中央处理单元，存储器，存储器输出选择电路和存储器输出总线的计算机系统中的多用途影子寄存器装置包括与存储器输出选择电路并联的影子寄存器。阴影寄存器被连接以从存储器输出总线接收存储器输出数据，并且响应于输出使能信号，以在影子寄存器输出总线上提供影子寄存器输出数据。提供多个功能块的影子寄存器功能逻辑块以相互排他的方式利用影子寄存器。

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